############################################################################
##
##  Xilinx, Inc. 2006            www.xilinx.com  
##  Tue October 17 9:21: 2006
##
##  
############################################################################
##  File name :       ddr_cntl_a.ucf
## 
##  Generated by  spartan3 released on April 03 2006
##  Description :     Constraints file
##                    targetted to xc3s4000-4 fg900 
##
############################################################################

############################################################################
# Clock constraints                                                        #
############################################################################
NET "infrastructure_top0/sys_clk_ibuf" TNM_NET = FFS(*) "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK"  7.518797  ns HIGH 50 %;

############################################################################
NET "infrastructure_top0/wait_200*" TIG;
NET "infrastructure_top0/wait_clk90" TIG;
NET "infrastructure_top0/sys_rst*"   TIG;

 NET "main_00/top0/reset90_r" TIG;

NET "main_00/top0/controller0/rst_calib*" TIG;
NET "main_00/top0/infrastructure0/delay_sel_val*" TIG;
NET "main_00/top0/infrastructure0/rst_calib*" TIG;
##INST "*/cal_top0/cal_ctl0/un1_tapForDqs*" TIG;
NET "infrastructure_top0/reset_in" TIG;
NET "infrastructure_top0/sys_rst*" TIG;
NET "*/controller0/rst0*" TIG;
NET "*/controller0/rst180*" TIG;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay*_col*" TIG;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed*" TIG;


#######################################################################################################################
# Calibration Circuit Constraints #
#######################################################################################################################
# Placement constraints for luts in tap delay ckt #
#######################################################################################################################

INST  "infrastructure_top0/cal_top0/tap_dly0/l0"  RLOC=X0Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/l0"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/l1"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/l2"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/l3"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/l4"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/l5"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/l6"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l7" RLOC=X1Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/l7"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  
INST  "infrastructure_top0/cal_top0/tap_dly0/l8" RLOC=X0Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/l8"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l9" RLOC=X0Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/l9"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l10" RLOC=X0Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/l10"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l11" RLOC=X0Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/l11"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l12" RLOC=X1Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/l12"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l13" RLOC=X1Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/l13"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 
INST  "infrastructure_top0/cal_top0/tap_dly0/l14" RLOC=X1Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/l14"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l15" RLOC=X1Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/l15"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l16" RLOC=X0Y2;
INST  "infrastructure_top0/cal_top0/tap_dly0/l16"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l17" RLOC=X0Y2;
INST  "infrastructure_top0/cal_top0/tap_dly0/l17"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l18" RLOC=X0Y3;
INST  "infrastructure_top0/cal_top0/tap_dly0/l18"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l19" RLOC=X0Y3;
INST  "infrastructure_top0/cal_top0/tap_dly0/l19"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l20" RLOC=X1Y2;
INST  "infrastructure_top0/cal_top0/tap_dly0/l20"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l21" RLOC=X1Y2;
INST  "infrastructure_top0/cal_top0/tap_dly0/l21"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l22" RLOC=X1Y3;
INST  "infrastructure_top0/cal_top0/tap_dly0/l22"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l23" RLOC=X1Y3;
INST  "infrastructure_top0/cal_top0/tap_dly0/l23"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l24" RLOC=X0Y0;
INST  "infrastructure_top0/cal_top0/tap_dly0/l24"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l25" RLOC=X0Y0;
INST  "infrastructure_top0/cal_top0/tap_dly0/l25"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
INST  "infrastructure_top0/cal_top0/tap_dly0/l26"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
INST  "infrastructure_top0/cal_top0/tap_dly0/l27"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
INST  "infrastructure_top0/cal_top0/tap_dly0/l28"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
INST  "infrastructure_top0/cal_top0/tap_dly0/l29"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
INST  "infrastructure_top0/cal_top0/tap_dly0/l30"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST  "infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
INST  "infrastructure_top0/cal_top0/tap_dly0/l31"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

#######################################################################################################################
# Placement constraints for first stage flops in tap delay ckt #
#######################################################################################################################
 
INST  "infrastructure_top0/cal_top0/tap_dly0/r0"    RLOC=X0Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/r0"   U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r1" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/r1"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r2" RLOC=X0Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/r2"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r3" RLOC=X0Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/r3"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r4" RLOC=X1Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/r4"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r5" RLOC=X1Y6;
INST  "infrastructure_top0/cal_top0/tap_dly0/r5"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r6" RLOC=X1Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/r6"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r7" RLOC=X1Y7;
INST  "infrastructure_top0/cal_top0/tap_dly0/r7"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r8" RLOC=X0Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/r8"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r9" RLOC=X0Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/r9"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r10" RLOC=X0Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/r10"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r11" RLOC=X0Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/r11"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r12" RLOC=X1Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/r12"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r13" RLOC=X1Y4;
INST  "infrastructure_top0/cal_top0/tap_dly0/r13"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r14" RLOC=X1Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/r14"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";

INST "infrastructure_top0/cal_top0/tap_dly0/r15" RLOC=X1Y5;
INST  "infrastructure_top0/cal_top0/tap_dly0/r15"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";