NET  "cntrl0_DDR_A[4]"	LOC = "F3" ;
NET  "cntrl0_DDR_A[3]"	LOC = "F2" ;
NET  "cntrl0_DDR_A[2]"	LOC = "E4" ;
NET  "cntrl0_DDR_A[1]"	LOC = "F5" ;
NET  "cntrl0_DDR_A[0]"	LOC = "E2" ;
NET  "cntrl0_DDR_BA[1]"	LOC = "E1" ;
NET  "cntrl0_DDR_BA[0]"	LOC = "D4" ;
NET  "cntrl0_DDR_CKE"	LOC = "D3" ;
NET  "cntrl0_DDR_CS_N"	LOC = "K9" ;
NET  "cntrl0_DDR_RAS_N"	LOC = "J6" ;
NET  "cntrl0_DDR_CAS_N"	LOC = "H5" ;
NET  "cntrl0_DDR_WE_N"	LOC = "D2" ;
NET  "reset_in"	LOC = "B5" ;
NET  "cntrl0_led_error_output1"	LOC = "A5" ;

#########################################################################
# MAXDELAY constraints                                                                        #
#########################################################################
    NET  "main_00/top0/data_path0/data_read_controller0/rst_dqs_div"        MAXDELAY = 3000ps;
NET  "main_00/top0/iobs0/controller_iobs0/rst_dqs_div*"         MAXDELAY = 3000ps;
NET  "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed*"         MAXDELAY = 3000ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_wr_en"              MAXDELAY = 2000ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_wr_addr[*]"               MAXDELAY = 3000ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_rd_addr*"               MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_rd_addr_r*"               MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/data_read0/fifo*_data_out[*]"                    MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/user_output_data[*]"                       MAXDELAY = 4200ps;
NET  "main_00/top0/write_en_val*"                            MAXDELAY = 4200ps;
NET  "main_00/top0/data_path0/dqs_int_delay_in*"  MAXDELAY = 700ps;
#########################################################################
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 0, location in tile: 0
NET "cntrl0_DDR_DQ[0]" LOC = R2;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit0" LOC = SLICE_X0Y96;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit0" LOC = SLICE_X0Y97;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 1, location in tile: 1
NET "cntrl0_DDR_DQ[1]" LOC = R3;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit1" LOC = SLICE_X2Y98;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit1" LOC = SLICE_X2Y99;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 2, location in tile: 0
NET "cntrl0_DDR_DQ[2]" LOC = R4;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit2" LOC = SLICE_X0Y98;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit2" LOC = SLICE_X0Y99;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 3, location in tile: 1
NET "cntrl0_DDR_DQ[3]" LOC = R5;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit3" LOC = SLICE_X2Y100;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit3" LOC = SLICE_X2Y101;
#############################################################
##  constraints for bit cntrl0_DDR_DQS, 0, location in tile: 1
NET "cntrl0_DDR_DQS[0]" LOC = R7;

## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X2Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X2Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X2Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X2Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X3Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X3Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X0Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X0Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X0Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X0Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X1Y103;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X1Y102;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;

########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = SLICE_X1Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = SLICE_X1Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = SLICE_X1Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = SLICE_X1Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = SLICE_X3Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = SLICE_X3Y98;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = SLICE_X3Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = SLICE_X3Y99;
INST "main_00/top0/data_path0/data_read_controller0/fifo_00_wr_en_inst" LOC = SLICE_X1Y101;
INST "main_00/top0/data_path0/data_read_controller0/fifo_01_wr_en_inst" LOC = SLICE_X3Y101;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 5, location in tile: 1
NET "cntrl0_DDR_DQ[5]" LOC = R9;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit5" LOC = SLICE_X2Y108;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit5" LOC = SLICE_X2Y109;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 4, location in tile: 0
NET "cntrl0_DDR_DQ[4]" LOC = R10;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit4" LOC = SLICE_X0Y108;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit4" LOC = SLICE_X0Y109;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 7, location in tile: 1
NET "cntrl0_DDR_DQ[7]" LOC = P2;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit7" LOC = SLICE_X2Y110;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit7" LOC = SLICE_X2Y111;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 6, location in tile: 0
NET "cntrl0_DDR_DQ[6]" LOC = P3;
INST "main_00/top0/data_path0/data_read0/strobe0/fifo_bit6" LOC = SLICE_X0Y110;
INST "main_00/top0/data_path0/data_read0/strobe0_n/fifo_bit6" LOC = SLICE_X0Y111;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 9, location in tile: 1
NET "cntrl0_DDR_DQ[9]" LOC = P6;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit1" LOC = SLICE_X2Y112;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit1" LOC = SLICE_X2Y113;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 8, location in tile: 0
NET "cntrl0_DDR_DQ[8]" LOC = P7;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit0" LOC = SLICE_X0Y112;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit0" LOC = SLICE_X0Y113;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 11, location in tile: 1
NET "cntrl0_DDR_DQ[11]" LOC = P9;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit3" LOC = SLICE_X2Y114;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit3" LOC = SLICE_X2Y115;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 10, location in tile: 0
NET "cntrl0_DDR_DQ[10]" LOC = P10;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit2" LOC = SLICE_X0Y114;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit2" LOC = SLICE_X0Y115;
#############################################################
##  constraints for bit cntrl0_DDR_DQS, 1, location in tile: 0
NET "cntrl0_DDR_DQS[1]" LOC = N2;

## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X2Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X2Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X2Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X2Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X3Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X3Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X0Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X0Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X0Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X0Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X1Y117;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X1Y116;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = G;

########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = SLICE_X1Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = SLICE_X1Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = SLICE_X1Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = SLICE_X1Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = SLICE_X3Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = SLICE_X3Y112;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = SLICE_X3Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = SLICE_X3Y113;
INST "main_00/top0/data_path0/data_read_controller0/fifo_10_wr_en_inst" LOC = SLICE_X1Y115;
INST "main_00/top0/data_path0/data_read_controller0/fifo_11_wr_en_inst" LOC = SLICE_X3Y115;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 13, location in tile: 1
NET "cntrl0_DDR_DQ[13]" LOC = N4;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit5" LOC = SLICE_X2Y120;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit5" LOC = SLICE_X2Y121;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 12, location in tile: 0
NET "cntrl0_DDR_DQ[12]" LOC = N5;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit4" LOC = SLICE_X0Y120;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit4" LOC = SLICE_X0Y121;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 15, location in tile: 1
NET "cntrl0_DDR_DQ[15]" LOC = N6;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit7" LOC = SLICE_X2Y122;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit7" LOC = SLICE_X2Y123;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 14, location in tile: 0