NET "cntrl0_DDR_DQ[14]" LOC = M5;
INST "main_00/top0/data_path0/data_read0/strobe1/fifo_bit6" LOC = SLICE_X0Y122;
INST "main_00/top0/data_path0/data_read0/strobe1_n/fifo_bit6" LOC = SLICE_X0Y123;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 17, location in tile: 1
NET "cntrl0_DDR_DQ[17]" LOC = N10;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit1" LOC = SLICE_X2Y126;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit1" LOC = SLICE_X2Y127;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 16, location in tile: 0
NET "cntrl0_DDR_DQ[16]" LOC = M10;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit0" LOC = SLICE_X0Y126;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit0" LOC = SLICE_X0Y127;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 19, location in tile: 1
NET "cntrl0_DDR_DQ[19]" LOC = M1;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit3" LOC = SLICE_X2Y128;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit3" LOC = SLICE_X2Y129;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 18, location in tile: 0
NET "cntrl0_DDR_DQ[18]" LOC = M4;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit2" LOC = SLICE_X0Y132;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit2" LOC = SLICE_X0Y133;
#############################################################
##  constraints for bit cntrl0_DDR_DQS, 2, location in tile: 0
NET "cntrl0_DDR_DQS[2]" LOC = M7;

## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/one" LOC = SLICE_X2Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/two" LOC = SLICE_X2Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/three" LOC = SLICE_X2Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/four" LOC = SLICE_X2Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/five" LOC = SLICE_X3Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/six" LOC = SLICE_X3Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col0/six" BEL = G;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/one" LOC = SLICE_X0Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/two" LOC = SLICE_X0Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/three" LOC = SLICE_X0Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/four" LOC = SLICE_X0Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/five" LOC = SLICE_X1Y135;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/six" LOC = SLICE_X1Y134;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay2_col1/six" BEL = G;

########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit0" LOC = SLICE_X1Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit1" LOC = SLICE_X1Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit2" LOC = SLICE_X1Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit3" LOC = SLICE_X1Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit0" LOC = SLICE_X3Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit1" LOC = SLICE_X3Y130;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit2" LOC = SLICE_X3Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit3" LOC = SLICE_X3Y131;
INST "main_00/top0/data_path0/data_read_controller0/fifo_20_wr_en_inst" LOC = SLICE_X1Y133;
INST "main_00/top0/data_path0/data_read_controller0/fifo_21_wr_en_inst" LOC = SLICE_X3Y133;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 21, location in tile: 1
NET "cntrl0_DDR_DQ[21]" LOC = M8;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit5" LOC = SLICE_X2Y136;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit5" LOC = SLICE_X2Y137;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 20, location in tile: 0
NET "cntrl0_DDR_DQ[20]" LOC = M9;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit4" LOC = SLICE_X0Y136;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit4" LOC = SLICE_X0Y137;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 23, location in tile: 1
NET "cntrl0_DDR_DQ[23]" LOC = L1;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit7" LOC = SLICE_X2Y138;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit7" LOC = SLICE_X2Y139;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 22, location in tile: 0
NET "cntrl0_DDR_DQ[22]" LOC = L2;
INST "main_00/top0/data_path0/data_read0/strobe2/fifo_bit6" LOC = SLICE_X0Y138;
INST "main_00/top0/data_path0/data_read0/strobe2_n/fifo_bit6" LOC = SLICE_X0Y139;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 25, location in tile: 1
NET "cntrl0_DDR_DQ[25]" LOC = L3;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit1" LOC = SLICE_X2Y142;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit1" LOC = SLICE_X2Y143;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 24, location in tile: 0
NET "cntrl0_DDR_DQ[24]" LOC = L4;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit0" LOC = SLICE_X0Y142;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit0" LOC = SLICE_X0Y143;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 27, location in tile: 1
NET "cntrl0_DDR_DQ[27]" LOC = L5;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit3" LOC = SLICE_X2Y144;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit3" LOC = SLICE_X2Y145;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 26, location in tile: 0
NET "cntrl0_DDR_DQ[26]" LOC = L6;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit2" LOC = SLICE_X0Y144;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit2" LOC = SLICE_X0Y145;
#############################################################
##  constraints for bit cntrl0_DDR_DQS, 3, location in tile: 0
NET "cntrl0_DDR_DQS[3]" LOC = L8;

## LUT location constraints for col 0
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/one" LOC = SLICE_X2Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/two" LOC = SLICE_X2Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/three" LOC = SLICE_X2Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/four" LOC = SLICE_X2Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/five" LOC = SLICE_X3Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/six" LOC = SLICE_X3Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col0/six" BEL = G;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/one" LOC = SLICE_X0Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/two" LOC = SLICE_X0Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/two" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/three" LOC = SLICE_X0Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/four" LOC = SLICE_X0Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/five" LOC = SLICE_X1Y147;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/six" LOC = SLICE_X1Y146;
INST "main_00/top0/data_path0/data_read_controller0/dqs_delay3_col1/six" BEL = G;

########################WRITE ADD & WRITE_EN##########
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit0" LOC = SLICE_X1Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit1" LOC = SLICE_X1Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit2" LOC = SLICE_X1Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit3" LOC = SLICE_X1Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit0" LOC = SLICE_X3Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit1" LOC = SLICE_X3Y142;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit2" LOC = SLICE_X3Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit3" LOC = SLICE_X3Y143;
INST "main_00/top0/data_path0/data_read_controller0/fifo_30_wr_en_inst" LOC = SLICE_X1Y145;
INST "main_00/top0/data_path0/data_read_controller0/fifo_31_wr_en_inst" LOC = SLICE_X3Y145;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 29, location in tile: 1
NET "cntrl0_DDR_DQ[29]" LOC = L10;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit5" LOC = SLICE_X2Y148;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit5" LOC = SLICE_X2Y149;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 28, location in tile: 0
NET "cntrl0_DDR_DQ[28]" LOC = K10;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit4" LOC = SLICE_X0Y148;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit4" LOC = SLICE_X0Y149;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 30, location in tile: 0
NET "cntrl0_DDR_DQ[30]" LOC = K3;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit6" LOC = SLICE_X0Y150;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit6" LOC = SLICE_X0Y151;
#############################################################
##  constraints for bit cntrl0_DDR_DQ, 31, location in tile: 1
NET "cntrl0_DDR_DQ[31]" LOC = K6;
INST "main_00/top0/data_path0/data_read0/strobe3/fifo_bit7" LOC = SLICE_X2Y154;
INST "main_00/top0/data_path0/data_read0/strobe3_n/fifo_bit7" LOC = SLICE_X2Y155;
#############################################################
##  constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1
NET "cntrl0_rst_dqs_div_in" LOC = N9;

## LUT location constraints for col 1
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/one" LOC = SLICE_X0Y125;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/one" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/two" LOC = SLICE_X0Y124;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/two" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/three" LOC = SLICE_X0Y125;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/three" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/four" LOC = SLICE_X1Y124;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/four" BEL = F;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/five" LOC = SLICE_X1Y124;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/five" BEL = G;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/six" LOC = SLICE_X1Y125;
INST "main_00/top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/six" BEL = G;
#############################################################
##  constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 1
NET "cntrl0_rst_dqs_div_out" LOC = N8;
#################################################################################