///////////////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved.////////////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_controller_iobs_0.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: This module contains the IOB instantiations for the controller module///////////////////////////////////////////////////////////////////////////////////////`include "ddr_cntl_a_parameters_0.v"    `timescale 1ns/100psmodule ddr_cntl_a_controller_iobs_0 (    clk0,    ddr_rasb_cntrl,       ddr_casb_cntrl,       ddr_web_cntrl,        ddr_cke_cntrl,        ddr_csb_cntrl,        ddr_address_cntrl,    ddr_ba_cntrl,         rst_dqs_div_int,      ddr_rasb,           ddr_casb,           ddr_web,            ddr_ba,             ddr_address,        ddr_cke,            ddr_csb,            rst_dqs_div,        rst_dqs_div_in,     rst_dqs_div_out   );      input    clk0; input    ddr_rasb_cntrl; input    ddr_casb_cntrl; input    ddr_web_cntrl;  input    ddr_cke_cntrl;  input    ddr_csb_cntrl;  input    [`row_address-1:0]ddr_address_cntrl;input    [`bank_address-1:0]ddr_ba_cntrl;    input    rst_dqs_div_int;  output    ddr_rasb;        output    ddr_casb;        output    ddr_web;         output    [`bank_address-1:0]ddr_ba;     output    [`row_address-1:0]ddr_address; output    ddr_cke;         output    ddr_csb;         output    rst_dqs_div;     input	  rst_dqs_div_in; output	  rst_dqs_div_out;   wire [`row_address-1:0] ddr_address_iob_reg;wire [`bank_address-1:0] ddr_ba_reg;wire ddr_web_q;wire ddr_rasb_q;wire ddr_casb_q;wire ddr_cke_q;              FD iob_web  (                .Q( ddr_web_q),                .D( ddr_web_cntrl),                .C(~clk0)           );                          FD iob_rasb  (                .Q( ddr_rasb_q),                .D( ddr_rasb_cntrl),                .C(~clk0)           );                             FD iob_casb  (                .Q( ddr_casb_q),                .D( ddr_casb_cntrl),                .C(~clk0)           );//---- ************************************* ----//----  Output buffers for control signals   ----//---- ************************************* ---- OBUF r16  (            .I( ddr_web_q),            .O( ddr_web)          ); OBUF r17  (            .I( ddr_rasb_q),            .O( ddr_rasb)          );           OBUF r18  (            .I( ddr_casb_q),            .O( ddr_casb)          );           OBUF r19  (            .I(ddr_csb_cntrl),            .O( ddr_csb)          );          FD iob_cke (            .Q(ddr_cke_q),            .D(ddr_cke_cntrl),                .C(~clk0)           );                OBUF r20(        .I(ddr_cke_q),        .O(ddr_cke)       );//---- ************************************* ----//----  Output buffers for address signals   ----//---- ************************************* ----	FD iob_addr0 (            .Q(ddr_address_iob_reg[0]),            .D(ddr_address_cntrl[0]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr1 (            .Q(ddr_address_iob_reg[1]),            .D(ddr_address_cntrl[1]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr2 (            .Q(ddr_address_iob_reg[2]),            .D(ddr_address_cntrl[2]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr3 (            .Q(ddr_address_iob_reg[3]),            .D(ddr_address_cntrl[3]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr4 (            .Q(ddr_address_iob_reg[4]),            .D(ddr_address_cntrl[4]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr5 (            .Q(ddr_address_iob_reg[5]),            .D(ddr_address_cntrl[5]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr6 (            .Q(ddr_address_iob_reg[6]),            .D(ddr_address_cntrl[6]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr7 (            .Q(ddr_address_iob_reg[7]),            .D(ddr_address_cntrl[7]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr8 (            .Q(ddr_address_iob_reg[8]),            .D(ddr_address_cntrl[8]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr9 (            .Q(ddr_address_iob_reg[9]),            .D(ddr_address_cntrl[9]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr10 (            .Q(ddr_address_iob_reg[10]),            .D(ddr_address_cntrl[10]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr11 (            .Q(ddr_address_iob_reg[11]),            .D(ddr_address_cntrl[11]),//          .C( clk180)            .C(~clk0)            ) ;	FD iob_addr12 (            .Q(ddr_address_iob_reg[12]),            .D(ddr_address_cntrl[12]),//          .C( clk180)            .C(~clk0)            ) ;	OBUF r0   (           .I(ddr_address_iob_reg[0]),           .O(ddr_address[0]));	OBUF r1   (           .I(ddr_address_iob_reg[1]),           .O(ddr_address[1]));	OBUF r2   (           .I(ddr_address_iob_reg[2]),           .O(ddr_address[2]));	OBUF r3   (           .I(ddr_address_iob_reg[3]),           .O(ddr_address[3]));	OBUF r4   (           .I(ddr_address_iob_reg[4]),           .O(ddr_address[4]));	OBUF r5   (           .I(ddr_address_iob_reg[5]),           .O(ddr_address[5]));	OBUF r6   (           .I(ddr_address_iob_reg[6]),           .O(ddr_address[6]));	OBUF r7   (           .I(ddr_address_iob_reg[7]),           .O(ddr_address[7]));	OBUF r8   (           .I(ddr_address_iob_reg[8]),           .O(ddr_address[8]));	OBUF r9   (           .I(ddr_address_iob_reg[9]),           .O(ddr_address[9]));	OBUF r10   (           .I(ddr_address_iob_reg[10]),           .O(ddr_address[10]));	OBUF r11   (           .I(ddr_address_iob_reg[11]),           .O(ddr_address[11]));	OBUF r12   (           .I(ddr_address_iob_reg[12]),           .O(ddr_address[12]));FD iob_ba1(            .Q(ddr_ba_reg[0]),            .D(ddr_ba_cntrl[0]),                .C(~clk0)            );                                                  FD iob_ba2(            .Q(ddr_ba_reg[1]),            .D(ddr_ba_cntrl[1]),                .C(~clk0)            );                                                    OBUF r14  (               .I(ddr_ba_reg[0]),               .O(ddr_ba[0])); OBUF r15  (               .I(ddr_ba_reg[1]),               .O(ddr_ba[1]));                        IBUF rst_iob_inbuf                     ( .I(rst_dqs_div_in),                     .O(rst_dqs_div));                              OBUF rst_iob_outbuf                   ( .I(rst_dqs_div_int),                   .O(rst_dqs_div_out));endmodule