`include "../rtl/ddr1_64_parameters_0.v"

`timescale 1ps / 1ps
//`timescale 1ns / 100ps



module ddr1_test_tb;

parameter CLOCK_PERIOD = 5000;
parameter HALF_CLK_PERIOD = 2500; 

reg clk    ;
wire clkb   ;
reg rst    ;
wire [`clk_width-1:0]ddr_clk;
wire [`clk_width-1:0]ddr_clkb;
wire [`data_strobe_width-1:0]ddr_dqs_fpga   ;
wire [`data_strobe_width-1:0]ddr_dqs_sdram  ;
wire [`data_width-1:0] ddr_dq_fpga   ;
wire [`data_width-1:0] ddr_dq_sdram  ;
wire ddr_cke           ;
wire ddr_csb           ;
wire ddr_rasb          ;
wire ddr_casb          ;
wire ddr_web           ;
wire [`data_mask_width-1:0]ddr_dm;
wire [1:0] ddr_ba         ;
wire [`row_address-1:0] ddr_address   ;

wire [2:0]CMD        ;
reg  enable_o          ;
reg  enable            ;
wire led_error_output1 ;
wire rst_dqs_div       ;
wire rst_dqs_div1;
   
wire gnd               ;
wire tmp               ;
wire tmp1              ;
wire [(2*`data_width)-1:0] read_data_out ;
wire [(2*`data_width)-1:0] lfsr_data_out ;                                                
                                                  
assign CMD = {ddr_rasb, ddr_casb , ddr_web};        
assign dip1 = 1'b1;     
assign dip2 = 1'b1;                                                                       
assign clkb = ~ clk;
assign gnd = 1'b0;

   assign #4000 rst_dqs_div1 =  rst_dqs_div;
    
always @(posedge clk)
  begin
     if (!rst)
       begin
	  enable_o <= 1'b0;
          enable <= 1'b0;
       end
    else if(CMD == 3'b100) // write
       enable_o <= 1'b0;
     else if(CMD == 3'b101) // read
       enable_o <= 1'b1;
     else
       enable_o <= enable_o;

     enable <= enable_o;
      
  end 
     

// During a READ

   assign #100 ddr_dqs_fpga  =  (enable) ?  ddr_dqs_sdram : 8'bz;
   assign #100 ddr_dq_fpga =  (enable) ? ddr_dq_sdram : 64'bz;
                 

// During a WRITE

   assign #50 ddr_dqs_sdram =  (!enable_o) ? ddr_dqs_fpga : 8'bz;
   assign ddr_dq_sdram = (!enable_o) ? ddr_dq_fpga : 64'bz;
  


ddr1_64    mem_interface_top  (
                              .reset_in			(rst),
					.SYS_CLK			(clk),
					.SYS_CLKb			(clkb),
					.cntrl0_rst_dqs_div_in		(rst_dqs_div),
					.cntrl0_rst_dqs_div_out		(rst_dqs_div),
					.cntrl0_DDR_CAS_N			(ddr_casb),
					.cntrl0_DDR_CKE			(ddr_cke),
					.cntrl0_led_error_output1	(led_error_output1),
					.cntrl0_DDR_CK		(ddr_clk), 
					.cntrl0_DDR_CK_N		(ddr_clkb), 
					.cntrl0_DDR_CS_N		(ddr_csb),
					.cntrl0_DDR_RAS_N		(ddr_rasb),
					.cntrl0_DDR_WE_N		(ddr_web),
					.cntrl0_DDR_A		(ddr_address),
					.cntrl0_DDR_DQS		(ddr_dqs_fpga),
					.cntrl0_DDR_BA		(ddr_ba),
					.cntrl0_DDR_DM		(ddr_dm),
					.cntrl0_DDR_DQ		(ddr_dq_fpga)
					);

ddr mt46v16m16_0 (
                                 .Dq    ( ddr_dq_sdram[15:0]),
                                 .Dqs   ( ddr_dqs_sdram[1:0]),
                                 .Addr  ( ddr_address),
                                 .Ba    ( ddr_ba),
                                 .Clk   ( ddr_clk[0]),
                                 .Clk_n ( ddr_clkb[0]),
                                 .Cke   ( ddr_cke),
                                 .Cs_n  ( ddr_csb),
                                 .Ras_n ( ddr_rasb),
                                 .Cas_n ( ddr_casb),
                                 .We_n  ( ddr_web),
                                 .Dm    ( ddr_dm[1:0])
                                 );
ddr mt46v16m16_1 (
                                 .Dq    ( ddr_dq_sdram[31:16]),
                                 .Dqs   ( ddr_dqs_sdram[3:2]),
                                 .Addr  ( ddr_address),
                                 .Ba    ( ddr_ba),
                                 .Clk   ( ddr_clk[1]),
                                 .Clk_n ( ddr_clkb[1]),
                                 .Cke   ( ddr_cke),
                                 .Cs_n  ( ddr_csb),
                                 .Ras_n ( ddr_rasb),
                                 .Cas_n ( ddr_casb),
                                 .We_n  ( ddr_web),
                                 .Dm    ( ddr_dm[3:2])
                                 );
ddr mt46v16m16_2 (
                                 .Dq    ( ddr_dq_sdram[47:32]),
                                 .Dqs   ( ddr_dqs_sdram[5:4]),
                                 .Addr  ( ddr_address),
                                 .Ba    ( ddr_ba),
                                 .Clk   ( ddr_clk[2]),
                                 .Clk_n ( ddr_clkb[2]),
                                 .Cke   ( ddr_cke),
                                 .Cs_n  ( ddr_csb),
                                 .Ras_n ( ddr_rasb),
                                 .Cas_n ( ddr_casb),
                                 .We_n  ( ddr_web),
                                 .Dm    ( ddr_dm[5:4])
                                 );


ddr mt46v16m16_3 (
                                 .Dq    ( ddr_dq_sdram[63:48]),
                                 .Dqs   ( ddr_dqs_sdram[7:6]),
                                 .Addr  ( ddr_address),
                                 .Ba    ( ddr_ba),
                                 .Clk   ( ddr_clk[3]),
                                 .Clk_n ( ddr_clkb[3]),
                                 .Cke   ( ddr_cke),
                                 .Cs_n  ( ddr_csb),
                                 .Ras_n ( ddr_rasb),
                                 .Cas_n ( ddr_casb),
                                 .We_n  ( ddr_web),
                                 .Dm    ( ddr_dm[7:6])
                                 );



//Clock Generation

initial clk <= 1'b0;
always #3750 clk <=  ~clk;


//  RESET Generation

initial
  begin
     rst <= 1'b0;
     #25000 rst <= 1'b1;
  end



  

endmodule