//////////////////////////////////////////////////////////////////////////////// Copyright (c) 2005 Xilinx, Inc.// This design is confidential and proprietary of Xilinx, All Rights Reserved./////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  / Vendor: Xilinx// \   \   \/ Version: 1.6//  \   \    Application : MIG//  /   /    Filename: ddr_cntl_a_lfsr32_0.v// /___/   /\ Date Last Modified:  Tue Jul 11 2006// \   \  /  \ Date Created: Mon May 2 2005//  \___\/\___\// Device: Spartan-3/3e// Design Name: DDR1_S3/S3e// Description: This module generates the user input data for hardware test ///////////////////////////////////////////////////////////////////////////////`timescale 1ns/100ps`include "ddr_cntl_a_parameters_0.v"module    ddr_cntl_a_lfsr32_0( 		clk,		rst,		lfsr_rst,		lfsr_ena,		lfsr_data_m,		lfsr_out                );                  input          clk;   input          rst;   input          lfsr_rst;   input          lfsr_ena;      output [((`data_mask_width*2)-1):0]	lfsr_data_m;   output [((`data_width*2)-1):0] lfsr_out;      reg  [7:0]    lfsr_r;   reg  [7:0]    lfsr_f;   assign lfsr_data_m = 16'b0;           assign lfsr_out = {	lfsr_r,	lfsr_r,	lfsr_r,	lfsr_r ,                   	lfsr_f,	lfsr_f,	lfsr_f,	lfsr_f		   };                          always @ (posedge clk)begin	if (rst == 1'b1)	begin		lfsr_r <= 'b0;		lfsr_f <= 'd1;	end	else if (lfsr_rst == 1'b1)		begin		lfsr_r <= 'b0;		lfsr_f <= 'd1;		end	else if (lfsr_ena == 1'b1)	begin		lfsr_r <= lfsr_r + 2;			lfsr_f <= lfsr_f + 2;		end	else	begin		lfsr_f <= lfsr_f ;		lfsr_r <= lfsr_r;	end	endendmodule