-- Xilinx Vhdl produced by program ngd2vhdl F.23-- Command: -rpw 100 -ar Structure -te DECODER_TIME_POST -xon false -w -log __projnav/ngd2vhdl.log dec_16b20b.nga DECODER_TIME_POST.vhd -- Input file: dec_16b20b.nga-- Output file: DECODER_TIME_POST.vhd-- Design name: dec_16b20b-- Xilinx: C:/Xilinx_WebPACK_51-- # of Entities: 1-- Device: XCR3128XL-6-VQ100-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,-- or used in any other manner other than simulation. This netlist uses simulation-- primitives which may not represent the true implementation of the device, however-- the netlist is functionally correct. Do not modify this file.-- Model for  ROC (Reset-On-Configuration) Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is  generic (InstancePath: STRING := "*";           WIDTH : Time := 100 ns);  port(O : out std_ulogic := '1') ;  attribute VITAL_LEVEL0 of ROC : entity is TRUE;end ROC;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;begin  ONE_SHOT : process  begin    if (WIDTH <= 0 ns) then       assert FALSE report       "*** Error: a positive value of WIDTH must be specified ***"       severity failure;    else       wait for WIDTH;       O <= '0';    end if;    wait;  end process ONE_SHOT;end ROC_V;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity DECODER_TIME_POST is  port (    clk : in STD_LOGIC := 'X';     frame_in_dec : in STD_LOGIC := 'X';     rst : in STD_LOGIC := 'X';     frame_out_dec : out STD_LOGIC;     ill_char_det : out STD_LOGIC;     serial_data : in STD_LOGIC_VECTOR ( 19 downto 0 );     decoded_data : out STD_LOGIC_VECTOR ( 15 downto 0 )   );end DECODER_TIME_POST;architecture Structure of DECODER_TIME_POST is  component ROC    generic (InstancePath: STRING := "*";             WIDTH : Time := 100 ns);    port (O : out STD_ULOGIC := '1');  end component;  signal decoded_data_0_MC_Q : STD_LOGIC;   signal decoded_data_0_MC_Q_tsim_ireg_Q : STD_LOGIC;   signal decoded_data_0_MC_D : STD_LOGIC;   signal lower_dec_prs_state_fft2 : STD_LOGIC;   signal lower_dec_prs_state_fft1 : STD_LOGIC;   signal lower_dec_hout : STD_LOGIC;   signal decoded_data_0_MC_D1_PT_0 : STD_LOGIC;   signal decoded_data_0_MC_D1 : STD_LOGIC;   signal decoded_data_0_MC_D2 : STD_LOGIC;   signal decoded_data_0_MC_UIM : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_Q : STD_LOGIC;   signal FOOBAR1_ctinst_0 : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_R_OR_PRLD : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_D : STD_LOGIC;   signal clk_II_FCLK : STD_LOGIC;   signal rst_II_UIM : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_D1 : STD_LOGIC;   signal frame_in_dec_II_UIM : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_D2_PT_0 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2 : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_D2 : STD_LOGIC;   signal lower_dec_prs_state_fft2_MC_D_TFF : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_Q : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_R_OR_PRLD : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_D : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_D1 : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_D2_PT_0 : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_D2 : STD_LOGIC;   signal lower_dec_prs_state_fft1_MC_D_TFF : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_Q : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_R_OR_PRLD : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_D : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_D1 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_0 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd1_MC_D2 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_Q : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_R_OR_PRLD : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_D : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_D1 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_D2_PT_0 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_dec_8b10b_prs_state_ffd2_MC_D2 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_Q : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_R_OR_PRLD : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_D : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_D1 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_D2_PT_0 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd1_MC_D2 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_Q : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_R_OR_PRLD : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_D : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_D1 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_D2_PT_0 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_err_chk_prs_state_ffd2_MC_D2 : STD_LOGIC;   signal lower_dec_hout_MC_Q : STD_LOGIC;   signal lower_dec_hout_MC_D : STD_LOGIC;   signal lower_dec_hout_MC_D1 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_0 : STD_LOGIC;   signal serial_data_1_II_UIM : STD_LOGIC;   signal serial_data_0_II_UIM : STD_LOGIC;   signal N_PZ_188 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_1 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_2 : STD_LOGIC;   signal serial_data_3_II_UIM : STD_LOGIC;   signal serial_data_2_II_UIM : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_3 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_4 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_5 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_6 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_7 : STD_LOGIC;   signal lower_dec_hout_MC_D2_PT_8 : STD_LOGIC;   signal lower_dec_hout_MC_D2 : STD_LOGIC;   signal N_PZ_188_MC_Q : STD_LOGIC;   signal N_PZ_188_MC_D : STD_LOGIC;   signal serial_data_5_II_UIM : STD_LOGIC;   signal serial_data_4_II_UIM : STD_LOGIC;   signal N_PZ_309 : STD_LOGIC;   signal N_PZ_188_MC_D1_PT_0 : STD_LOGIC;   signal N_PZ_188_MC_D1 : STD_LOGIC;   signal N_PZ_188_MC_D2 : STD_LOGIC;   signal N_PZ_309_MC_Q : STD_LOGIC;   signal N_PZ_309_MC_D : STD_LOGIC;   signal serial_data_7_II_UIM : STD_LOGIC;   signal serial_data_6_II_UIM : STD_LOGIC;   signal N_PZ_309_MC_D1_PT_0 : STD_LOGIC;   signal N_PZ_309_MC_D1 : STD_LOGIC;   signal N_PZ_309_MC_D2 : STD_LOGIC;   signal decoded_data_10_MC_Q : STD_LOGIC;   signal decoded_data_10_MC_Q_tsim_ireg_Q : STD_LOGIC;   signal decoded_data_10_MC_D : STD_LOGIC;   signal upper_dec_prs_state_fft2 : STD_LOGIC;   signal upper_dec_prs_state_fft1 : STD_LOGIC;   signal upper_dec_fout : STD_LOGIC;   signal decoded_data_10_MC_D1_PT_0 : STD_LOGIC;   signal decoded_data_10_MC_D1 : STD_LOGIC;   signal decoded_data_10_MC_D2 : STD_LOGIC;   signal decoded_data_10_MC_UIM : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_Q : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_R_OR_PRLD : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_D : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_D1 : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2 : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_D2 : STD_LOGIC;   signal upper_dec_prs_state_fft2_MC_D_TFF : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_Q : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_R_OR_PRLD : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_D : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_D1 : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_D2 : STD_LOGIC;   signal upper_dec_prs_state_fft1_MC_D_TFF : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_Q : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_R_OR_PRLD : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_D : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_D1 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd1_MC_D2 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_Q : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_R_OR_PRLD : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_D : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_D1 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_dec_8b10b_prs_state_ffd2_MC_D2 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_Q : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_R_OR_PRLD : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_D : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_D1 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd1_MC_D2 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_Q : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_R_OR_PRLD : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_D : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_D1 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_err_chk_prs_state_ffd2_MC_D2 : STD_LOGIC;   signal upper_dec_fout_MC_Q : STD_LOGIC;   signal upper_dec_fout_MC_D : STD_LOGIC;   signal upper_dec_fout_MC_D1 : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_0 : STD_LOGIC;   signal upper_dec_hin : STD_LOGIC;   signal upper_dec_jin : STD_LOGIC;   signal upper_dec_fin : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_1 : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_2 : STD_LOGIC;   signal N_PZ_189 : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_3 : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_4 : STD_LOGIC;   signal upper_dec_gin : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_5 : STD_LOGIC;   signal upper_dec_fout_MC_D2_PT_6 : STD_LOGIC;   signal upper_dec_fout_MC_D2 : STD_LOGIC;   signal upper_dec_hin_MC_Q : STD_LOGIC;   signal upper_dec_hin_MC_D : STD_LOGIC;   signal serial_data_11_II_UIM : STD_LOGIC;   signal upper_dec_hin_MC_D1_PT_0 : STD_LOGIC;   signal upper_dec_hin_MC_D1 : STD_LOGIC;   signal upper_dec_hin_MC_D2 : STD_LOGIC;   signal upper_dec_jin_MC_Q : STD_LOGIC;