?? uart_tx_tb.vhd
字號:
sout_chk(5, "01011010", '1', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '0', 1.5, True, CLK_PERIOD*16, SOUT);
-- Test 3 ----------------------------------------------------
-- 5-bit data, odd parity, 1 stop
sout_chk(5, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 4 ----------------------------------------------------
-- 5-bit data, odd parity, 1.5 stop
sout_chk(5, "01010101", '0', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '1', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '0', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '1', 1.5, True, CLK_PERIOD*16, SOUT);
-- Test 5 ----------------------------------------------------
-- 5-bit data, stick even parity, 1 stop
sout_chk(5, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 6 ----------------------------------------------------
-- 5-bit data, stick even parity, 1.5 stop
sout_chk(5, "01010101", '0', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '0', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '0', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '0', 1.5, True, CLK_PERIOD*16, SOUT);
-- Test 7 ----------------------------------------------------
-- 5-bit data, stick odd parity, 1 stop
sout_chk(5, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 8 ----------------------------------------------------
-- 5-bit data, stick odd parity, 1.5 stop
sout_chk(5, "01010101", '1', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '1', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '1', 1.5, True, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '1', 1.5, True, CLK_PERIOD*16, SOUT);
-- Test 9 ----------------------------------------------------
-- 5-bit data, no parity, 1 stop
sout_chk(5, "01010101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
-- Test 10 ---------------------------------------------------
-- 5-bit data, no parity, 1.5 stop
sout_chk(5, "01010101", '0', 1.5, false, CLK_PERIOD*16, SOUT);
sout_chk(5, "10101010", '0', 1.5, false, CLK_PERIOD*16, SOUT);
sout_chk(5, "01011010", '0', 1.5, false, CLK_PERIOD*16, SOUT);
sout_chk(5, "10100101", '0', 1.5, false, CLK_PERIOD*16, SOUT);
-- Test 11 ---------------------------------------------------
-- 6-bit data, even parity, 1 stop
sout_chk(6, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 12 ---------------------------------------------------
-- 6-bit data, even parity, 2 stop
sout_chk(6, "01010101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 13 ---------------------------------------------------
-- 6-bit data, odd parity, 1 stop
sout_chk(6, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 14 ---------------------------------------------------
-- 6-bit data, odd parity, 2 stop
sout_chk(6, "01010101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 15 ---------------------------------------------------
-- 6-bit data, stick even parity, 1 stop
sout_chk(6, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 16 ---------------------------------------------------
-- 6-bit data, stick even parity, 2 stop
sout_chk(6, "01010101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 17 ---------------------------------------------------
-- 6-bit data, stick odd parity, 1 stop
sout_chk(6, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 18 ---------------------------------------------------
-- 6-bit data, stick odd parity, 2 stop
sout_chk(6, "01010101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 19 ---------------------------------------------------
-- 6-bit data, no parity, 1 stop
sout_chk(6, "01010101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(6, "10100101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
-- Test 20 ---------------------------------------------------
-- 6-bit data, no parity, 2 stop
sout_chk(6, "01010101", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(6, "10101010", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(6, "01011010", '0', 2.0, false, CLK_PERIOD*16, SOUT);
-- Test 21 ---------------------------------------------------
-- 7-bit data, even parity, 1 stop
sout_chk(7, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 22 ---------------------------------------------------
-- 7-bit data, even parity, 2 stop
sout_chk(7, "01010101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 23 ---------------------------------------------------
-- 7-bit data, odd parity, 1 stop
sout_chk(7, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 24 ---------------------------------------------------
-- 7-bit data, odd parity, 2 stop
sout_chk(7, "01010101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
-- 7-bit data, stick even parity, 1 stop
sout_chk(7, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 26 ---------------------------------------------------
-- 7-bit data, stick even parity, 2 stop
sout_chk(7, "01010101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 27 ---------------------------------------------------
-- 7-bit data, stick odd parity, 1 stop
sout_chk(7, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 28 ---------------------------------------------------
-- 7-bit data, stick odd parity, 2 stop
sout_chk(7, "01010101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 29 ---------------------------------------------------
-- 7-bit data, no parity, 1 stop
sout_chk(7, "01010101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
-- Test 30 ---------------------------------------------------
-- 7-bit data, no parity, 2 stop
sout_chk(7, "01010101", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(7, "10101010", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(7, "01011010", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(7, "10100101", '0', 2.0, false, CLK_PERIOD*16, SOUT);
-- Test 31 ---------------------------------------------------
-- 8-bit data, even parity, 1 stop
sout_chk(8, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 32 ---------------------------------------------------
-- 8-bit data, even parity, 2 stop
sout_chk(8, "01010101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 33 ---------------------------------------------------
-- 8-bit data, odd parity, 1 stop
sout_chk(8, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 34 ---------------------------------------------------
-- 8-bit data, odd parity, 2 stop
sout_chk(8, "01010101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 35 ---------------------------------------------------
-- 8-bit data, stick even parity, 1 stop
sout_chk(8, "01010101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '0', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '0', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 36 ---------------------------------------------------
-- 8-bit data, stick even parity, 2 stop
sout_chk(8, "01010101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '0', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '0', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 37 ---------------------------------------------------
-- 8-bit data, stick odd parity, 1 stop
sout_chk(8, "01010101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '1', 1.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '1', 1.0, True, CLK_PERIOD*16, SOUT);
-- Test 38 ---------------------------------------------------
-- 8-bit data, stick odd parity, 2 stop
sout_chk(8, "01010101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '1', 2.0, True, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '1', 2.0, True, CLK_PERIOD*16, SOUT);
-- Test 39 ---------------------------------------------------
-- 8-bit data, no parity, 1 stop
sout_chk(8, "01010101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '0', 1.0, false, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '0', 1.0, false, CLK_PERIOD*16, SOUT);
-- Test 40 ---------------------------------------------------
-- 8-bit data, no parity, 2 stop
sout_chk(8, "01010101", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(8, "10101010", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(8, "01011010", '0', 2.0, false, CLK_PERIOD*16, SOUT);
sout_chk(8, "10100101", '0', 2.0, false, CLK_PERIOD*16, SOUT);
-- end of tests ----------------------------------------------
wait;
end process Sout_Chk_Proc;
-----------------------------------------------------------------------
-- Test UART Transmitter/Receiver Functions
-----------------------------------------------------------------------
UART_Stim_Proc : process
variable i : integer;
begin
-- Reset and Intialization
MR <= '1';
CS <= '0';
ADSn <= '1';
A <= "111";
DIN <= "11111111";
SIN <= '1';
CTSn <= '1';
DCDn <= '1';
DSRn <= '1';
RIn <= '1';
wait for (9.5*CLK_PERIOD);
MR <= '0';
wait for (0.5*CLK_PERIOD);
wait until falling_edge(PCLK);
-- Test 1 ----------------------------------------------------
-- 5-bit data, even parity, 1 stop
TestID <= 1;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 0, 1 stop bit
-- bit 1 : 0, 5 data bit (bit[1-0]="00")
-- bit 0 : 0, 5 data bit (bit[1-0]="00")
write_reg (LCR,"00011000",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
-- Write 2nd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);
-- Write 3rd data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);
-- Write 4th data to THR
if (TxRDYn = '1') then
wait until TxRDYn = '0';
end if;
write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);
wait until falling_edge(PCLK);
-- Test 2 ----------------------------------------------------
-- 5-bit data, even parity, 1.5 stop
TestID <= 2;
i := 1;
loop
if (i < WAIT_TIMEOUT) then
wait for CLK_PERIOD;
-- Read LSR (check if "TEMT" flag at bit 6 is set)
read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
exit when regData_readBack(6) = '1';
i := i + 1;
else
assert (false) report"Data Transmission Failed"
severity failure;
end if;
end loop;
wait for (16*CLK_PERIOD);
-- LCR Intialization
-- bit 6 : 0, do not set break
-- bit 5 : 0, not stick parity
-- bit 4 : 1, even parity selected
-- bit 3 : 1, parity enabled
-- bit 2 : 1, 1.5 stop bit
-- bit 1 : 0, 5 data bit (bit[1-0]="00")
-- bit 0 : 0, 5 data bit (bit[1-0]="00")
write_reg (LCR,"00011100",CS,ADSn,WRn,A,DIN);
-- Write 1st data to THR
write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);
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