?? intface.vhd
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-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2001 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Permission:
--
-- Lattice Semiconductor grants permission to use this code for use
-- in synthesis for any Lattice programmable logic product. Other
-- use of this code, including the selling or duplication of any
-- portion is strictly prohibited.
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 408-826-6000 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
--
-- Project: Universal Asynchronous Receiver Transmitter
-- File: intface.vhd
-- Title: intface
-- Design Library: IEEE
-- Dependencies: IEEE.std_logic_1164.all
-- IEEE.std_logic_unsigned.all
-- Description: VHDL File for UART Controller Interface Module.
--
-- <Global reset and clock>
-- Reset : Master reset
-- Clk16X : UART internal clock
--
-- <Processor interface>
-- A : Address bus
-- DIN : Data bus input
-- DOUT : Data but output
-- ADSn : Address strobe
-- CS : Chip Select
-- RDn : Read
-- WRn : Write
-- DDIS : Driver disable
-- INTR : Interrupt
--
-- <Registers>
-- RBR : Receiver Buffer Register
-- THR : Transmitter Holding Register
-- MSR : Modem Status Register
-- MCR : Modem Control Register
--
-- <Rising edge of registers read/write strobes>
-- RbrRDn_re : one Clk16X width pulse indicating rising edge of RbrRDn_r
-- ThrWRn_re : one Clk16X width pulse indicating rising edge of ThrWRn_r
-- LsrRDn_re : one Clk16X width pulse indicating rising edge of LsrRDn_r
-- MsrRDn_re : one Clk16X width pulse indicating rising edge of MsrRDn_r
--
-- <Receiver/Transmitter control>
-- Databits : "00"=5-bit, "01"=6-bit, "10"=7-bit, "11"=8-bit
-- Stopbits : "00"=1-bit, "01"=1.5-bit(5-bit data),
-- "10"=2-bit(6,7,8-bit data)
-- ParityEnable: '0'=Parity Bit Enable, '1'=Parity Bit Disable
-- ParityEven : '0'=Even Parity Selected, '1'=Odd Parity Selected
-- ParityStick : '0'=Stick Parity Disable, '1'=Stick Parity Enable
-- TxBreak : '0'=Disable BREAK assertion, '1'=Assert BREAK
--
-- <Receiver/Transmitter status>
-- RxRDY : RBR data is ready to be read
-- OverrunErr : Overrun error
-- ParityErr : Parity error
-- FrameErr : Frame error
-- BreakInt : BREAK interrupt
-- THRE : THR is empty
-- TEMT : Both THR and TSR are empty
--
-- --------------------------------------------------------------------
--
-- Revision History :
-- --------------------------------------------------------------------
-- Ver :| Author :| Mod. Date :| Changes Made:
-- V1.1 :| J.H. :| 06/19/01 :| Support ispMACH 5000VG
-- V1.0 :| D.W. & J.H. :| 06/01/01 :| First Release
-- --------------------------------------------------------------------
--
--
------------------------------------------------------------------------------
-- GENERAL REGISTER: --
-------------------------- --
-- ================================================================= --
-- | ADDRESS A[2:0] | REGISTER | IMPLEMENT | --
-- ================================================================= --
-- | $000 (READ) | RBR (RECEIVER BUFFER REGISTER) | Y | --
-- ----------------------------------------------------------------- --
-- | $000 (WRITE) | THR (TRANSMIT HOLD REGISTER) | Y | --
-- ================================================================= --
-- | $001 (WRITE) | IER (INTERRUPT ENABLE REGISTER) | Y | --
-- ================================================================= --
-- | $010 (READ) | IIR (INTERRUPT ID REGISTER) | Y | --
-- ================================================================= --
-- | $011 (WRITE) | LCR (LINE CONTROL REGISTER) | Y | --
-- ================================================================= --
-- | $100 (WRITE) | MCR (MODEM CONTROL REGISTER) | Y | --
-- ================================================================= --
-- | $101 (READ) | LSR (LINE STATUS REGISTER) | Y | --
-- ================================================================= --
-- | $110 (READ) | MSR (MODEM STATUS REGISTER) | Y | --
-- ================================================================= --
-- | $111 (READ/WRITE) | SCR (SCRATCHPAD REGISTER) | N | --
-- ================================================================= --
-- --
-- NOTE: By using Lattice ISP solution, the Baud Rate can be
-- re-configured even when the device is soldered on the board. --
-- Therefore the Baud Rate register set is omitted. --
-- --
-- Because each Lattice ispLSI device has a embedded UES register, --
-- the Scratchpad register can be omitted too. --
-- --
------------------------------------------------------------------------------
-- REGISTER BIT FIELDS: --
---------------------------- --
-- --
-- ============================ --
-- | LSR (LINE STATUS REGISTER) | --
-- ============================================================== --
-- | 0 | TEMT | THRE | BI | FE | PE | OE | RxRDY | --
-- ============================================================== --
-- --
-- RxRDY : RECEIVE DATA READY --
-- OE : OVERRUN ERROR --
-- PE : PARITY ERROR --
-- FE : FRAMING ERROR --
-- BI : BREAK INTERRUPT --
-- THRE : TRASMITTER HOLDING REGISTER EMPTY --
-- TEMT : TRASMITTER EMPTY --
-- --
-- --
-- RxRDY: The data received flag is set to 1 at the successful --
-- completion of a byte receive cycle. It is automatically --
-- cleared to 0 when the Rx Data Register is read. If a new byte --
-- is received before an Rx Data Register read, the over run flag --
-- will be set to 1. If (SR) status option is set the UART will --
-- ignore all further incoming bytes until the Rx Data Register --
-- has been read. --
-- --
-- OE: It indicates that the data in RBR was not read by the CPU --
-- before the next character arrived, thereby destroying the the --
-- previous character. The OE indicator is set to 1 upon --
-- detection of an overrun condition and reset whenever the CPU --
-- reads the contents of LSR --
-- --
-- PE: The parity error flag is set to 1 if an invalid parity bit is --
-- encountered. It is automatically cleared to 0 when the CPU --
-- reads the contents of Line Status Register. --
-- --
-- FE: The framing error flag is set to 1 if an invalid stop bit is --
-- encountered. It is automatically cleared to 0 when the CPU --
-- reads the contents of Line Status Register. --
-- --
-- BI: The start bit error flag is set to 1 if an invalid start bit --
-- is encountered. It is automatically cleared to 0 when the CPU --
-- reads the contents of Line Status Register. --
-- --
-- THRE: The Transmit Holding Register Empty flag indicate that the --
-- UART is ready to accept a new character for transmission. In --
-- addition this bit cause the UART issue an interrupt to the CPU --
-- when the THRE interrupt enable is set to high --
-- --
-- TEMT: The Transmitter Empty indicator is set to '1' whenever --
-- whenever the Transmitter Holding Register and the Transmitter --
-- Shifting Register are both empty. It is reset to '0' whenever --
-- either the Transmitter Holding register or Transmitter Shift --
-- Register contains a character --
-- --
-- ================================ --
-- | LCR (LINE CONTROL REGISTER) | --
-- =============================================================== --
-- | DLAB | SB | SP | EPS | PEN | STB | WLS1 | WLS0 | --
-- =============================================================== --
-- --
-- WLS1-WLS0: WORD LENGTH SELECT 00 = 5 DATA BITS --
-- 01 = 6 DATA BITS --
-- 10 = 7 DATA BITS --
-- 11 = 8 DATA BITS --
-- --
-- STB: NUMBER OF STOP BITS 0 = 1 STOP BIT (DEFAULT) --
-- 1 = 1.5 STOP BITS (DATA LENGTH 5 BITS) --
-- 1 = 2 STOP BITS (DATA LENGTH 6,7,8 BITS) --
-- --
-- PEN: PARITY ENABLE --
-- EPS: EVEN PARITY SELECT --
-- SP: SET PARITY --
-- SP EPS PEN PARITY SELECTION --
-- X X 0 NO PARITY --
-- 0 0 1 ODD PARITY --
-- 0 1 1 EVEN PARITY --
-- 1 0 1 FORCE PARITY "1" --
-- 1 1 1 FORCE PARITY "0" --
-- --
-- SB: SET BREAK When enable the Break control bit causes a break --
-- condition to be transmitted (the TX output is forced to a logic --
-- 0 state). This condition exits until disabled by resetting this --
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