?? intface.vhd
字號(hào):
-- bit to a logic 0. --
-- --
-- DLAB: DIVISOR LATCH ACCESS BIT: 0 = Divisor latch disable (default) --
-- 1 = Divisor latch enabled --
-- Note: Because we use ISP solution to reconfigure Baud Rate, --
-- this bit is omitted as well as the Baud Rate Register. --
-- --
-- ============================= --
-- | IIR (INTERRUPT ID REGISTER) | --
-- =================================================================== --
-- | 0 | 0 | 0 | 0 | INT 2 | INT 1 | INT 0 | INT STAT | --
-- =================================================================== --
-- --
-- PRIOTITY LEVEL BIT-3 BIT-2 BIT-1 BIT-0 SOURCE OF INTERRUPT --
-- NONE 0 0 0 1 NONE --
-- HIGHEST 0 1 1 0 LSR (OE/PE/FE/BI) --
-- 2nd 0 1 0 0 RxRDY (Receiver Data Ready)--
-- 3rd 0 0 1 0 THRE (THR Empty) --
-- 4th 0 0 0 0 MSR (Modem Status Register)--
-- --
-- In the 16450 Mode Bit-3 is 0. --
-- --
-- ================================= --
-- | IER (INTERRUPT ENABLE REGISTER) | --
-- =============================================================== --
-- | 0 | 0 | 0 | 0 | MSI | RLSI | THRI | RHRI | --
-- =============================================================== --
-- --
-- RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disble) --
-- THRI: Transmitter Hold Register Interrupt (1 = Enalbe, 0 = Disble) --
-- RLSI: Receiver Line Status Interrupt (1 = Enalble, 0 = Disble) --
-- MSI: Modem Status Interrupt (1 = Enable, 0 = Disble) --
-- --
-- ============================= --
-- | MSR (MODEM STATUS REGISTER) | --
-- =============================================================== --
-- | DCD | RI | DSR | CTS | DDCD | TERI | DDSR | DCTS | --
-- =============================================================== --
-- --
-- DCD: Data Carrier Detect --
-- RI: Ring Indicator --
-- DSR: Data Set Ready --
-- CTS: Clear To Send --
-- DDCD: Delta Data Carrier Detect --
-- TERI: Trailing Edge Ring Indicator --
-- DDSR: Delta Data Set Ready --
-- DCTS: Delta Clear to Send --
-- Bit0-3 are set to '1' whenever a control input from the MODEM changes --
-- state, and an Modem Stauts. Interrupt is generated. They are reset to --
-- '0' whenever the CPU reads the Modem Status Register. --
-- --
-- ============================== --
-- | MCR (MODEM CONTROL REGISTER) | --
-- =============================================================== --
-- | 0 | 0 | 0 | LOOP* | OUT2* | OUT1* | RTS | DTR | --
-- =============================================================== --
-- --
-- DTR: Data Terminal Ready --
-- RTS: Request To Send --
-- OUT1: Auxiliary User-defined Output 1 (Not Implemented) --
-- OUT2: Auxiliary User-defined Output 2 (Not Implemented) --
-- LOOP: Local Loopback for diagnostic testing of the UART --
-- (Not Implemented) --
-- --
-- Note: OUT1, OUT2 and LOOP are not implemented --
-- --
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity Intface is
port (
-- Global reset and clock
Reset : in std_logic; -- Master reset
Clk16X : in std_logic; -- UART internal clock
-- Processor interface
A : in std_logic_vector(2 downto 0); -- Address bus
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data but output
ADSn : in std_logic; -- Address strobe
CS : in std_logic; -- Chip Select
RDn : in std_logic; -- Read
WRn : in std_logic; -- Write
DDIS : out std_logic; -- Driver disable
INTR : out std_logic; -- Interrupt
-- Registers
RBR : in std_logic_vector(7 downto 0); -- Receiver Buffer Reg
THR : out std_logic_vector(7 downto 0); -- Transmitter Holding Reg
MSR : in std_logic_vector(7 downto 0); -- Modem Status Reg
MCR : out std_logic_vector(1 downto 0); -- Modem Control Reg
-- Rising edge of registers read/write strobes
RbrRDn_re : out std_logic; -- pulse indicating rising of RbrRDn_r
ThrWRn_re : out std_logic; -- pulse indicating rising of ThrWRn_r
LsrRDn_re : inout std_logic; -- pulse indicating rising of LsrRDn_r
MsrRDn_re : inout std_logic; -- pulse indicating rising of MsrRDn_r
-- Receiver/Transmitter control
Databits : out std_logic_vector(1 downto 0);
Stopbits : out std_logic_vector(1 downto 0);
ParityEnable: out std_logic;
ParityEven : out std_logic;
ParityStick : out std_logic;
TxBreak : out std_logic;
-- Receiver/Transmitter status
RxRDY : in std_logic;
OverrunErr : in std_logic;
ParityErr : in std_logic;
FrameErr : in std_logic;
BreakInt : in std_logic;
THRE : in std_logic;
TEMT : in std_logic
);
end Intface;
architecture Intface_a of Intface is
signal ADDR_s : std_logic_vector(2 downto 0); -- Latched address bus
signal CS_r : std_logic; -- Latched CS signal
signal WRn_cs : std_logic; -- Write strobe qualified by latched CS signal
signal RDn_cs : std_logic; -- Read strobe qualified by latched CS signal
signal LSR : std_logic_vector(6 downto 0);
signal LCR : std_logic_vector(6 downto 0);
signal IIR : std_logic_vector(3 downto 0);
signal IER : std_logic_vector(3 downto 0);
signal ThrWRn_r : std_logic; -- THR write strobe
signal RbrRDn_r : std_logic; -- RBR read strobe
signal LsrRDn_r : std_logic; -- LSR read strobe
signal MsrRDn_r : std_logic; -- MSR read strobe
signal IirRDn_r : std_logic; -- IIR read strobe
signal IirRDn_re : std_logic; -- Rising edge of IIR read strobe
signal ThrWRn1_r : std_logic; -- 1-clock Delayed version for edge detection
signal ThrWRn2_r : std_logic; -- 2-clock Delayed version for edge detection
signal RbrRDn1_r : std_logic; -- 1-clock Delayed version for edge detection
signal RbrRDn2_r : std_logic; -- 2-clock Delayed version for edge detection
signal LsrRDn1_r : std_logic; -- 1-clock Delayed version for edge detection
signal LsrRDn2_r : std_logic; -- 2-clock Delayed version for edge detection
signal MsrRDn1_r : std_logic; -- 1-clock Delayed version for edge detection
signal MsrRDn2_r : std_logic; -- 2-clock Delayed version for edge detection
signal IirRDn1_r : std_logic; -- 1-clock Delayed version for edge detection
signal IirRDn2_r : std_logic; -- 2-clock Delayed version for edge detection
signal RxRDY_Int : std_logic;
signal THRE_Int : std_logic;
signal DataErr_Int : std_logic;
signal Modem_Int : std_logic;
signal DataErr : std_logic;
signal ModemStat : std_logic;
-- State Machine Definition
type state_typ is (idle, int0, int1, int2, int3);
signal Int_State : state_typ;
-- UART Registers Address Map
constant A_RBR : std_logic_vector(2 downto 0) := "000";
constant A_THR : std_logic_vector(2 downto 0) := "000";
constant A_IER : std_logic_vector(2 downto 0) := "001";
constant A_IIR : std_logic_vector(2 downto 0) := "010";
constant A_LCR : std_logic_vector(2 downto 0) := "011";
constant A_MCR : std_logic_vector(2 downto 0) := "100";
constant A_LSR : std_logic_vector(2 downto 0) := "101";
constant A_MSR : std_logic_vector(2 downto 0) := "110";
-- Attributes for ispMACH5000VG to get higher performance
-- These can be removed when the UART design is targeted to other devices.
ATTRIBUTE SYN_KEEP : integer;
ATTRIBUTE SYN_KEEP OF RbrRDn1_r : SIGNAL IS 1;
ATTRIBUTE OPT : string;
ATTRIBUTE OPT OF RbrRDn1_r : SIGNAL IS "KEEP";
begin
--------------------------------------------------------------------------------
-- Address Bus Latch
--------------------------------------------------------------------------------
Addr_Latch_Proc: process(Reset, ADSn, A)
begin
if (Reset='1') then
ADDR_s <= (others=>'0');
elsif (ADSn='0') then
ADDR_s <= A;
end if;
end process Addr_Latch_Proc;
--------------------------------------------------------------------------------
-- Chip Select Latch
--------------------------------------------------------------------------------
Chip_Select_Latch_Proc: process(Reset, CS, ADSn)
begin
if (Reset='1') then
CS_r <= '0';
elsif (ADSn='0') then
CS_r <= CS;
end if;
end process Chip_Select_Latch_Proc;
--------------------------------------------------------------------------------
-- Registers Read/Write Control Signals
--------------------------------------------------------------------------------
-- Read/Write strobes qualified by latched CS signal CS_r
WRn_cs <= WRn when (CS_r='1') else '1';
RDn_cs <= RDn when (CS_r='1') else '1';
-- Registers read/write strobes
ThrWRn_r <= '1' when (Reset='1') else WRn_cs when (ADDR_s=A_THR) else '1';
RbrRDn_r <= '1' when (Reset='1') else RDn_cs when (ADDR_s=A_RBR) else '1';
LsrRDn_r <= '1' when (Reset='1') else RDn_cs when (ADDR_s=A_LSR) else '1';
MsrRDn_r <= '1' when (Reset='1') else RDn_cs when (ADDR_s=A_MSR) else '1';
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