library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cdu99  is
	port (
			clk,reset:in std_logic;
      		count11:out std_logic_vector (3 downto 0);
      		count12:out std_logic_vector (3 downto 0); 
      		count13:out std_logic_vector (3 downto 0)); 
end cdu99 ;

architecture aa of cdu99 is
	begin
	process(clk,reset)
	variable mm:std_logic_vector(11 downto 0);
	begin
	if reset='1' then
		mm:="000000000000";
	elsif clk'event and clk='1' then
		if mm(3 downto 0)="1001" then
		mm:=mm+7;
		else 
		mm:=mm+1; 
		end if;
		if mm(7 downto 4)="1010" then
		mm:=mm+"01100000"; 
		end if;
	end if;
	count11<=mm(3 downto 0);
	count12<=mm(7 downto 4);
	count13<=mm(11 downto 8);
	end process;
end aa;