/****************************************************************************************** * Company: Beihang University CNS/ATM Lab * Engineer: hanjian * * Create Date: 15:16:50 03/21/2007 * Design Name: Project_SDRAMCtrl * Module Name: CommandResponse * Project Name: Project_SDRAMCtrl * Target Devices: Spartan3--XC3S1000 * Tool versions: *   TopDesigner: Altium Designer 6.0 *        Editor: SlickEdit 11.0 *     Simulator: ModelSim 6.0d *   Synthetizer: Synplify Pro 8.1 *    Downloader: Xilinx ISE 8.1i * Description: CommandResponse * * Dependencies: * * Revision: * Revision 0.01 - File Created * Additional Comments: *****************************************************************************************/ //Include files`include "../Module/Timescale.v"module CMDParse     (       sysClk_I,   //system clock       nRESET_I,   //global reset       address_I,       read_I,       write_I,       refresh_I,       precharge_I,       loadmode_I,       cmdACK_O,       SDRAM_CLK_O,       Saddress_O,       Baddress_O,       CKE_O,       CS_O,       RAS_O,       CAS_O,       WE_O,       OE_O,    );    //Parameter    //Input port    input sysClk_I;    input [`ADDR_WIDTH-1:0] address_I;    input nRESET_I;    input read_I;    input write_I;    input refresh_I;    input precharge_I;    input loadmode_I;        //Output port    output cmdACK_O;    output [`ADDR_WIDTH-1:0] Saddress_O;    output [`ADDR_WIDTH-1:0] Baddress_O;    output SDRAM_CLK_O;    output CKE_O;    output CS_O;    output RAS_O;    output CAS_O;    output WE_O;    output OE_O;    //Register    reg cmdACK_O;    reg [`ADDR_WIDTH-1:0] Saddress_O;    reg [`ADDR_WIDTH-1:0] Baddress_O;    reg SDRAM_CLK_O;    reg CKE_O;    reg CS_O;    reg RAS_O;    reg CAS_O;    reg WE_O;    reg OE_O;    //Internal register   // reg [`ADDR_WIDTH-1:0] mode_R;  //  reg [2:0] refreshCnt_R;  //  reg [31:0] Cnt_R;/*  * Always block *//*  * State machine */    //Fsm    always @(posedge sysClk_I or negedge nRESET_I) begin        if (!nRESET_I) begin            //Reset all segment            cmdACK_O <= #`Tp 0;            address_O <= #`Tp 0;            read_O <= #`Tp 0;            write_O <= #`Tp 0;            refresh_O <= #`Tp 0;            precharge_O <= #`Tp 0;            loadmode_O <= #`Tp 0;            Cnt_R <= #`Tp 0;            mode_R <= #`Tp 0;        end        else begin            case (CMD_I)             endcase        endendmodule