------------------------------------------------------------------------------
-- 
--  Name:  acl_gen.vhd  
-- 
--  Description:  This module generates ack signal upon detection of cs_l signal
-- 
--  $Revision: 1.0 $          
--  
--  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
--
------------------------------------------------------------------------------
-- Permission:
--
--   Lattice Semiconductor grants permission to use this code for use
--   in synthesis for any Lattice programmable logic product.  Other
--   use of this code, including the selling or duplication of any
--   portion is strictly prohibited.
--
-- Disclaimer:
--
--   This VHDL or Verilog source code is intended as a design reference
--   which illustrates how these types of functions can be implemented.
--   It is the user's responsibility to verify their design for
--   consistency and functionality through the use of formal
--   verification methods.  Lattice Semiconductor provides no warranty
--   regarding the use or functionality of this code.
------------------------------------------------------------------------------
--
--    Lattice Semiconductor Corporation
--    5555 NE Moore Court
--    Hillsboro, OR 97124
--    U.S.A
--
--    TEL: 1-800-Lattice (USA and Canada)
--    408-826-6000 (other locations)
--
--    web: http://www.latticesemi.com/
--    email: techsupport@latticesemi.com
-- 
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned."-";
use ieee.std_logic_unsigned."+";


--Module  ack_gen
--This modules sole purpose is to respond to uP transactions 4 clock cycles
--  after cs_l is active by asserting ack_l



entity ack_gen is port(clk   : in std_logic;
                       rst_l : in std_logic;
                       cs_l  : in std_logic;
                       ack_l : out std_logic);
end ack_gen;            


architecture behave of ack_gen is
-----------------------------------------------------------------------
-- registers & wires

signal count: std_logic_vector(2 downto 0);

begin

--// ack_l starts off deasserted or high
--// then when the count(2) = '1' 
--// then ack_l = '0'


ack : process(clk,rst_l)
begin 
  if (rst_l = '0') then 
        ack_l <= '1';
  elsif(rising_edge(clk)) then
      if(count(2) = '1') then 
        ack_l <= '0';
      else  
        ack_l <= '1';
      end if;
  end if;
end process;

-- whiles cs_l = '0' the counter will count
-- up to "100" and hold until cs_l = '1' 
cnt : process(clk,rst_l)
begin 
  if (rst_l = '0') then 
        count <= "000";
  elsif(rising_edge(clk)) then
     if ((cs_l = '0') and (count <= "011")) then 
        count <= count + 1;
     elsif(cs_l = '1') then
        count <= "000";
     else
        count <= count;
     end if;
  end if;
end process;

end behave;

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