?? class.ptf
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file_mod = "Tue Jun 13 16:42:46 CST 2006";
quartus_map_start = "Tue Jun 13 16:48:23 CST 2006";
quartus_map_finished = "Tue Jun 13 16:48:27 CST 2006";
#found 1 valid modules
WRAPPER freedev_ps2
{
CLASS freedev_ps2
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
filepath = "D:/FreeDevADB/dsp_bais/freedev_ps2/hdl/freedev_ps2.v";
}
}
top_module_name = "freedev_ps2";
emit_system_h = "0";
}
MODULE_DEFAULTS global_signals
{
class = "freedev_ps2";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT rst
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT irq
{
width = "1";
width_expression = "";
direction = "output";
type = "irq";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT chipselect
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT read
{
width = "1";
width_expression = "";
direction = "input";
type = "read";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT write
{
width = "1";
width_expression = "";
direction = "input";
type = "write";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT address
{
width = "2";
width_expression = "";
direction = "input";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT readdata
{
width = "16";
width_expression = "";
direction = "output";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT writedata
{
width = "16";
width_expression = "";
direction = "input";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT ps2_clk
{
width = "1";
width_expression = "";
direction = "inout";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT ps2_data
{
width = "1";
width_expression = "";
direction = "inout";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "freedev_ps2";
technology = "imported components";
}
}
SOPC_Builder_Version = "0.0";
}
}
}
FILE ps2_keyboard_interface.v
{
file_mod = "Mon Jun 12 06:35:02 CST 2006";
quartus_map_start = "Tue Jun 13 16:48:53 CST 2006";
quartus_map_finished = "Tue Jun 13 16:48:58 CST 2006";
#found 1 valid modules
WRAPPER ps2_keyboard_interface
{
CLASS ps2_keyboard_interface
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
filepath = "D:/working/ps2/ps2_keyboard_interface.v";
}
}
top_module_name = "ps2_keyboard_interface";
emit_system_h = "0";
}
MODULE_DEFAULTS global_signals
{
class = "ps2_keyboard_interface";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT ps2_clk
{
width = "1";
width_expression = "";
direction = "inout";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT ps2_data
{
width = "1";
width_expression = "";
direction = "inout";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rx_extended
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rx_released
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rx_shift_key_on
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rx_scan_code
{
width = "8";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rx_ascii
{
width = "8";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT rx_data_ready
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT tx_data
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
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