//---------------------------------------------------------//杭州自由電子科技PS2鍵盤模塊//作者：柳軍勝//電話：0571-85084089//網址：www.freefpga.com//郵件：jhljs@hotmail.com//開發日期：20060607//簡要說明：//   0、本模塊在OpenCores ps2 ip cores基礎上改成Avalone slave設備//	  1、由設備生成PS2時鐘//	  2、該模塊中使用主時鐘50M//   3、例化了OPENCORES的PS2 core。       //---------------------------------------------------------`timescale 1ns/100psmodule freedev_ps2(clk,rst,irq,chipselect,read,write,address,readdata,writedata,                    ps2_clk,ps2_data);input clk;         // master clkinput rst;         // resetoutput irq;        // interrupt requestreg irq;input chipselect;		     // chip selectinput read;             // read signalinput write;            // write signalinput [1:0]address;	    // addressoutput [15:0]readdata;	 // out datainput  [15:0]writedata;	// in  datareg [15:0]readdata;inout	ps2_clk;	         // ps2 clockinout	ps2_data;	        // ps2 data	//================================= clk時鐘域:avalone slave 接口部分  ==============================	// 寄存器定義	reg [15:0] mode_reg;      // modele register         address 00	reg [15:0] command_reg;   // command register        address 01		wire [15:0] state;        // state register          address 10	// 總線讀信號	wire wacc = chipselect & write;	// 總線寫信號	wire racc = chipselect & read;	// 寫寄存器	always @(posedge clk )	if (rst)	begin		mode_reg    <= #1 16'h0;		command_reg <= #1 16'h0;	end	else	    if ( wacc )		begin	      		case ( address ) // synopsis parallel_case				2'b00 : mode_reg    <= #1 writedata;				2'b01 : command_reg <= #1 writedata;		         				default: ;	      		endcase		end		always @(posedge clk)	begin	if( racc )		case (address) // synopsis parallel_case			2'b00: readdata <= #1 mode_reg;			2'b01: readdata <= #1 command_reg;			2'b10: readdata <= #1 state;			2'b11: readdata <= #1 data;		endcase	end			//=========================== OPENCORES PS2 CORE INSTANCE =========================================	wire rx_extended;	wire rx_released;	wire rx_shift_key_on;	wire [7:0] rx_scan_code;	wire [7:0] rx_ascii;	wire rx_data_ready;	// 讀鍵盤信號生成	wire rx_read = (racc && (address==2'b11)) ? 1:0 ;	// 鍵盤數據	wire [15:0] data; 	assign data = {rx_scan_code[7:0],rx_ascii[7:0]};		wire [7:0]tx_data ;	assign tx_data = writedata[7:0];	wire tx_write = (wacc && (address==2'b11)) ? 1:0 ;		wire tx_write_ack_o;	wire tx_error_no_keyboard_ack;   assign state = {10'h0,rx_extended,rx_released,rx_shift_key_on,rx_data_ready,tx_write_ack_o,tx_error_no_keyboard_ack};	  ps2_keyboard_interface the_ps2(   .clk(clk),   .reset(rst),   .ps2_clk(ps2_clk),   .ps2_data(ps2_data),   .rx_extended(rx_extended),   .rx_released(rx_released),   .rx_shift_key_on(rx_shift_key_on),   .rx_scan_code(rx_scan_code),   .rx_ascii(rx_ascii),   .rx_data_ready(rx_data_ready),       // rx_read_o   .rx_read(rx_read),                   // rx_read_ack_i   .tx_data(tx_data),   .tx_write(tx_write),   .tx_write_ack_o(tx_write_ack_o),   .tx_error_no_keyboard_ack(tx_error_no_keyboard_ack)  );		endmodule