?? pcm.rpt
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Project Information e:\work\no.1\pro\pcm\pcm.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 04/28/2007 10:10:22
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
PCM
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
pcm EPM7032LC44-6 9 11 0 26 16 81 %
User Pins: 9 11 0
Project Information e:\work\no.1\pro\pcm\pcm.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\work\no.1\pro\pcm\pcm.rpt
** FILE HIERARCHY **
|lpm_add_sub:95|
|lpm_add_sub:95|addcore:adder|
|lpm_add_sub:95|addcore:adder|addcore:adder0|
|lpm_add_sub:95|altshift:result_ext_latency_ffs|
|lpm_add_sub:95|altshift:carry_ext_latency_ffs|
|lpm_add_sub:95|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:200|
|lpm_add_sub:200|addcore:adder|
|lpm_add_sub:200|addcore:adder|addcore:adder0|
|lpm_add_sub:200|altshift:result_ext_latency_ffs|
|lpm_add_sub:200|altshift:carry_ext_latency_ffs|
|lpm_add_sub:200|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:545|
|lpm_add_sub:545|addcore:adder|
|lpm_add_sub:545|addcore:adder|addcore:adder0|
|lpm_add_sub:545|altshift:result_ext_latency_ffs|
|lpm_add_sub:545|altshift:carry_ext_latency_ffs|
|lpm_add_sub:545|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
***** Logic for device 'pcm' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
d d d
a a a
t t t
a a a a a
b b b d d
u u u V G G G c G d d
s s s C N N N l N r r
2 1 0 C D D D k D 3 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
databus3 | 7 39 | addr4
databus4 | 8 38 | addr0
databus6 | 9 37 | addr5
GND | 10 36 | addr6
databus7 | 11 35 | VCC
databus5 | 12 EPM7032LC44-6 34 | addr1
ad_select | 13 33 | RESERVED
digit_select | 14 32 | RESERVED
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
ser_clk | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R s
E E E E N C E E E E e
S S S S D C S S S S r
E E E E E E E E i
R R R R R R R R a
V V V V V V V V l
E E E E E E E E _
D D D D D D D D d
a
t
a
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 11/16( 68%) 13/16( 81%) 22/36( 61%)
B: LC17 - LC32 16/16(100%) 8/16( 50%) 5/16( 31%) 19/36( 52%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 19/32 ( 59%)
Total logic cells used: 26/32 ( 81%)
Total shareable expanders used: 16/32 ( 50%)
Total Turbo logic cells used: 26/32 ( 81%)
Total shareable expanders not available (n/a): 2/32 ( 6%)
Average fan-in: 6.84
Total fan-in: 178
Total input pins required: 9
Total output pins required: 11
Total bidirectional pins required: 0
Total logic cells required: 26
Total flipflops required: 16
Total product terms required: 74
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 16
Synthesized logic cells: 6/ 32 ( 18%)
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
4 (1) (A) INPUT 0 0 0 0 0 0 1 databus0
5 (2) (A) INPUT 0 0 0 0 0 0 1 databus1
6 (3) (A) INPUT 0 0 0 0 0 0 1 databus2
7 (4) (A) INPUT 0 0 0 0 0 0 1 databus3
8 (5) (A) INPUT 0 0 0 0 0 0 1 databus4
12 (8) (A) INPUT 0 0 0 0 0 0 1 databus5
9 (6) (A) INPUT 0 0 0 0 0 0 1 databus6
11 (7) (A) INPUT 0 0 0 0 0 0 1 databus7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
38 20 B FF t 0 0 0 0 3 9 6 addr0 (:46)
34 23 B FF t 0 0 0 0 4 8 6 addr1 (:45)
40 18 B FF t 0 0 0 0 5 7 6 addr2 (:44)
41 17 B FF t 0 0 0 0 6 6 6 addr3 (:43)
39 19 B FF t 0 0 0 0 7 5 6 addr4 (:42)
37 21 B FF t 0 0 0 0 8 4 6 addr5 (:41)
36 22 B FF t 0 0 0 0 9 3 6 addr6 (:40)
13 9 A OUTPUT t 1 0 1 0 7 0 0 ad_select
14 10 A OUTPUT t 0 0 0 0 7 0 0 digit_select
17 12 A FF + t 0 0 0 0 4 1 3 ser_clk (:26)
28 28 B FF t 2 1 0 0 14 0 0 serial_data
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(4) 1 A SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2
(21) 16 A SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node3
(8) 5 A DFFE + t 0 0 0 0 5 1 3 divide13 (:22)
(6) 3 A DFFE + t 0 0 0 0 5 1 4 divide12 (:23)
(7) 4 A TFFE + t 0 0 0 0 1 1 4 divide11 (:24)
(12) 8 A TFFE + t 0 0 0 0 0 1 5 divide10 (:25)
(27) 29 B TFFE t 0 0 0 0 3 8 3 cnt82 (:27)
(33) 24 B TFFE t 0 0 0 0 2 8 4 cnt81 (:28)
(32) 25 B TFFE t 0 0 0 0 1 8 5 cnt80 (:29)
(5) 2 A SOFT s t 12 0 0 5 11 0 1 ~489~1
(26) 30 B SOFT s t 1 0 0 1 10 1 0 ~510~1
(25) 31 B SOFT s t 3 1 1 0 12 1 0 ~511~1
(24) 32 B SOFT s t 0 0 0 0 7 0 1 ~942~1
(31) 26 B SOFT s t 1 1 0 1 7 1 0 ~945~1
(29) 27 B SOFT s t 0 0 0 1 7 0 1 ~958~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC9 ad_select
| +----------------- LC10 digit_select
| | +--------------- LC1 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2
| | | +------------- LC16 |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node3
| | | | +----------- LC12 ser_clk
| | | | | +--------- LC5 divide13
| | | | | | +------- LC3 divide12
| | | | | | | +----- LC4 divide11
| | | | | | | | +--- LC8 divide10
| | | | | | | | | +- LC2 ~489~1
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> - - - - - - * - - - | * - | <-- |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2
LC16 -> - - - - - * - - - - | * - | <-- |LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node3
LC5 -> - - - * * * * - - - | * - | <-- divide13
LC3 -> - - * * * * * - - - | * - | <-- divide12
LC4 -> - - * * * * * * - - | * - | <-- divide11
LC8 -> - - * * * * * * * - | * - | <-- divide10
Pin
43 -> - - - - - - - - - - | - - | <-- clk
4 -> - - - - - - - - - * | * - | <-- databus0
5 -> - - - - - - - - - * | * - | <-- databus1
6 -> - - - - - - - - - * | * - | <-- databus2
7 -> - - - - - - - - - * | * - | <-- databus3
8 -> - - - - - - - - - * | * - | <-- databus4
LC20 -> * * - - - - - - - * | * * | <-- addr0
LC23 -> * * - - - - - - - * | * * | <-- addr1
LC18 -> * * - - - - - - - * | * * | <-- addr2
LC17 -> * * - - - - - - - * | * * | <-- addr3
LC19 -> * * - - - - - - - * | * * | <-- addr4
LC21 -> * * - - - - - - - * | * * | <-- addr5
LC22 -> * * - - - - - - - * | * * | <-- addr6
LC29 -> - - - - - - - - - * | * * | <-- cnt82
LC24 -> - - - - - - - - - * | * * | <-- cnt81
LC25 -> - - - - - - - - - * | * * | <-- cnt80
LC32 -> - - - - - - - - - * | * - | <-- ~942~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC20 addr0
| +----------------------------- LC23 addr1
| | +--------------------------- LC18 addr2
| | | +------------------------- LC17 addr3
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