?? pcm.rpt
字號:
| | | | +----------------------- LC19 addr4
| | | | | +--------------------- LC21 addr5
| | | | | | +------------------- LC22 addr6
| | | | | | | +----------------- LC28 serial_data
| | | | | | | | +--------------- LC29 cnt82
| | | | | | | | | +------------- LC24 cnt81
| | | | | | | | | | +----------- LC25 cnt80
| | | | | | | | | | | +--------- LC30 ~510~1
| | | | | | | | | | | | +------- LC31 ~511~1
| | | | | | | | | | | | | +----- LC32 ~942~1
| | | | | | | | | | | | | | +--- LC26 ~945~1
| | | | | | | | | | | | | | | +- LC27 ~958~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC20 -> * * * * * * * * - - - * * * * * | * * | <-- addr0
LC23 -> - * * * * * * * - - - * * * * * | * * | <-- addr1
LC18 -> - - * * * * * * - - - * * * * * | * * | <-- addr2
LC17 -> - - - * * * * * - - - * * * * * | * * | <-- addr3
LC19 -> - - - - * * * * - - - * * * * * | * * | <-- addr4
LC21 -> - - - - - * * * - - - * * * * * | * * | <-- addr5
LC22 -> - - - - - - * * - - - * * * * * | * * | <-- addr6
LC29 -> * * * * * * * * * - - * * - - - | * * | <-- cnt82
LC24 -> * * * * * * * * * * - * * - - - | * * | <-- cnt81
LC25 -> * * * * * * * * * * * * * - - - | * * | <-- cnt80
LC30 -> - - - - - - - * - - - - - - - - | - * | <-- ~510~1
LC31 -> - - - - - - - * - - - - - - - - | - * | <-- ~511~1
LC26 -> - - - - - - - * - - - - - - - - | - * | <-- ~945~1
LC27 -> - - - - - - - - - - - - * - - - | - * | <-- ~958~1
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
12 -> - - - - - - - - - - - - - - - * | - * | <-- databus5
9 -> - - - - - - - - - - - * - - - - | - * | <-- databus6
11 -> - - - - - - - - - - - - - - * - | - * | <-- databus7
LC12 -> - - - - - - - * * * * - - - - - | - * | <-- ser_clk
LC2 -> - - - - - - - - - - - - * - - - | - * | <-- ~489~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\work\no.1\pro\pcm\pcm.rpt
pcm
** EQUATIONS **
clk : INPUT;
databus0 : INPUT;
databus1 : INPUT;
databus2 : INPUT;
databus3 : INPUT;
databus4 : INPUT;
databus5 : INPUT;
databus6 : INPUT;
databus7 : INPUT;
-- Node name is 'addr0' = 'cnt1280'
-- Equation name is 'addr0', location is LC020, type is output.
addr0 = TFFE( VCC, _EQ001, VCC, VCC, VCC);
_EQ001 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'addr1' = 'cnt1281'
-- Equation name is 'addr1', location is LC023, type is output.
addr1 = TFFE( addr0, _EQ002, VCC, VCC, VCC);
_EQ002 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'addr2' = 'cnt1282'
-- Equation name is 'addr2', location is LC018, type is output.
addr2 = TFFE( _EQ003, _EQ004, VCC, VCC, VCC);
_EQ003 = addr0 & addr1;
_EQ004 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'addr3' = 'cnt1283'
-- Equation name is 'addr3', location is LC017, type is output.
addr3 = TFFE( _EQ005, _EQ006, VCC, VCC, VCC);
_EQ005 = addr0 & addr1 & addr2;
_EQ006 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'addr4' = 'cnt1284'
-- Equation name is 'addr4', location is LC019, type is output.
addr4 = TFFE( _EQ007, _EQ008, VCC, VCC, VCC);
_EQ007 = addr0 & addr1 & addr2 & addr3;
_EQ008 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'addr5' = 'cnt1285'
-- Equation name is 'addr5', location is LC021, type is output.
addr5 = TFFE( _EQ009, _EQ010, VCC, VCC, VCC);
_EQ009 = addr0 & addr1 & addr2 & addr3 & addr4;
_EQ010 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'addr6' = 'cnt1286'
-- Equation name is 'addr6', location is LC022, type is output.
addr6 = TFFE( _EQ011, _EQ012, VCC, VCC, VCC);
_EQ011 = addr0 & addr1 & addr2 & addr3 & addr4 & addr5;
_EQ012 = !cnt80 & !cnt81 & !cnt82;
-- Node name is 'ad_select'
-- Equation name is 'ad_select', location is LC009, type is output.
ad_select = LCELL( _EQ013 $ !addr6);
_EQ013 = !addr0 & !addr1 & addr2 & !addr3 & !addr4 & addr5 & addr6
# !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6
# !addr2 & !addr3 & !addr4 & addr5 & addr6
# !addr5 & addr6;
-- Node name is ':29' = 'cnt80'
-- Equation name is 'cnt80', location is LC025, type is buried.
cnt80 = TFFE( VCC, ser_clk, VCC, VCC, VCC);
-- Node name is ':28' = 'cnt81'
-- Equation name is 'cnt81', location is LC024, type is buried.
cnt81 = TFFE( cnt80, ser_clk, VCC, VCC, VCC);
-- Node name is ':27' = 'cnt82'
-- Equation name is 'cnt82', location is LC029, type is buried.
cnt82 = TFFE( _EQ014, ser_clk, VCC, VCC, VCC);
_EQ014 = cnt80 & cnt81;
-- Node name is 'digit_select'
-- Equation name is 'digit_select', location is LC010, type is output.
digit_select = LCELL( _EQ015 $ addr6);
_EQ015 = !addr0 & !addr1 & !addr3 & !addr4 & addr6
# !addr2 & !addr3 & !addr4 & addr6
# !addr5 & addr6;
-- Node name is ':25' = 'divide10'
-- Equation name is 'divide10', location is LC008, type is buried.
divide10 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':24' = 'divide11'
-- Equation name is 'divide11', location is LC004, type is buried.
divide11 = TFFE( divide10, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':23' = 'divide12'
-- Equation name is 'divide12', location is LC003, type is buried.
divide12 = DFFE( _EQ016 $ _LC001, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = divide10 & divide11 & !divide12 & divide13 & _LC001;
-- Node name is ':22' = 'divide13'
-- Equation name is 'divide13', location is LC005, type is buried.
divide13 = DFFE( _EQ017 $ _LC016, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = divide10 & divide11 & !divide12 & divide13 & _LC016;
-- Node name is 'ser_clk' = 'serial_clk'
-- Equation name is 'ser_clk', location is LC012, type is output.
ser_clk = TFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = divide10 & divide11 & !divide12 & divide13;
-- Node name is 'serial_data' = ':10'
-- Equation name is 'serial_data', type is output
serial_data = DFFE( _EQ019 $ VCC, ser_clk, VCC, VCC, VCC);
_EQ019 = !cnt80 & !cnt81 & !cnt82 & !_LC026 & _X001
# !_LC030 & !_LC031 & _X002;
_X001 = EXP(!addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6);
_X002 = EXP(!cnt80 & !cnt81 & !cnt82);
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC001', type is buried
_LC001 = LCELL( divide12 $ _EQ020);
_EQ020 = divide10 & divide11;
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC016', type is buried
_LC016 = LCELL( divide13 $ _EQ021);
_EQ021 = divide10 & divide11 & divide12;
-- Node name is '~489~1'
-- Equation name is '~489~1', location is LC002, type is buried.
-- synthesized logic cell
_LC002 = LCELL( _EQ022 $ _EQ023);
_EQ022 = !addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
cnt80 & cnt81 & !cnt82
# cnt80 & cnt81 & !cnt82 & !databus4 & _X003;
_X003 = EXP( addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6);
_EQ023 = _X004 & _X005 & _X006 & _X007 & _X008 & _X009 & _X010 &
_X011 & _X012 & _X013 & _X014;
_X004 = EXP( addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
cnt82 & !_LC032);
_X005 = EXP(!addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
cnt80 & !cnt81 & cnt82);
_X006 = EXP(!cnt80 & cnt81 & cnt82 & !databus1 & !_LC032);
_X007 = EXP( addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
!cnt80 & !_LC032);
_X008 = EXP(!cnt80 & !cnt82 & !databus0 & !_LC032);
_X009 = EXP(!cnt81 & !cnt82 & !databus0 & !_LC032);
_X010 = EXP( cnt80 & !cnt81 & cnt82 & !databus2);
_X011 = EXP(!cnt80 & !cnt81 & cnt82 & !databus3 & !_LC032);
_X012 = EXP( addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
!cnt81 & !_LC032);
_X013 = EXP( cnt80 & cnt81 & cnt82 & !databus0 & !_LC032);
_X014 = EXP( cnt82 & !databus0 & !databus1 & !databus2 & !databus3 & !_LC032);
-- Node name is '~510~1'
-- Equation name is '~510~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ024 $ GND);
_EQ024 = !addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
cnt80 & !cnt81 & !cnt82
# cnt80 & !cnt81 & !cnt82 & databus6 & _X015;
_X015 = EXP(!addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6);
-- Node name is '~511~1'
-- Equation name is '~511~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ025 $ _EQ026);
_EQ025 = !cnt80 & cnt81 & !cnt82 & !_LC027 & _X001 & _X016
# cnt82 & !_LC002 & _X016
# cnt80 & !_LC002 & _X016
# !cnt81 & !_LC002 & _X016;
_X001 = EXP(!addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6);
_X016 = EXP( cnt80 & !cnt81 & !cnt82);
_EQ026 = _X016;
_X016 = EXP( cnt80 & !cnt81 & !cnt82);
-- Node name is '~942~1'
-- Equation name is '~942~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ027 $ GND);
_EQ027 = !addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6;
-- Node name is '~945~1'
-- Equation name is '~945~1', location is LC026, type is buried.
-- synthesized logic cell
_LC026 = LCELL( _EQ028 $ GND);
_EQ028 = addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
_X001
# databus7 & _X001;
_X001 = EXP(!addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6);
-- Node name is '~958~1'
-- Equation name is '~958~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ029 $ databus5);
_EQ029 = addr0 & !addr1 & !addr2 & !addr3 & !addr4 & !addr5 & !addr6 &
databus5;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\work\no.1\pro\pcm\pcm.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,030K
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