<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
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     behavior or data corruption.  It is strongly advised that
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<messages>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net a0/_n0017 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net a0/N3 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

</messages>