Release 8.1i - xst I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.66 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.66 s | Elapsed : 0.00 / 1.00 s --> Reading design: ps2_lcd1602_1.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis     5.1) Advanced HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "ps2_lcd1602_1.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "ps2_lcd1602_1"Output Format                      : NGCTarget Device                      : xc3s400-5-pq208---- Source OptionsTop Module Name                    : ps2_lcd1602_1Automatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NORTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : ps2_lcd1602_1.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "F:/FPGA/ps2_lcd_1602/ps2.vhd" in Library work.Entity <ps2> compiled.Entity <ps2> (Architecture <behavioral>) compiled.Compiling vhdl file "F:/FPGA/ps2_lcd_1602/LCD1602.vhd" in Library work.Architecture behavioral of Entity lcd1602 is up to date.Compiling vhdl file "F:/FPGA/ps2_lcd_1602/ps2_lcd1602_1.vhd" in Library work.Architecture behavioral of Entity ps2_lcd1602_1 is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <ps2_lcd1602_1> (Architecture <behavioral>).Entity <ps2_lcd1602_1> analyzed. Unit <ps2_lcd1602_1> generated.Analyzing Entity <ps2> (Architecture <behavioral>).WARNING:Xst:819 - "F:/FPGA/ps2_lcd_1602/ps2.vhd" line 109: The following signals are missing in the process sensitivity list:   parbit.WARNING:Xst:819 - "F:/FPGA/ps2_lcd_1602/ps2.vhd" line 165: The following signals are missing in the process sensitivity list:   hit_cnt.Entity <ps2> analyzed. Unit <ps2> generated.Analyzing Entity <LCD1602> (Architecture <behavioral>).WARNING:Xst:790 - "F:/FPGA/ps2_lcd_1602/LCD1602.vhd" line 95: Index value(s) does not match array range, simulation mismatch.Entity <LCD1602> analyzed. Unit <LCD1602> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <LCD1602>.    Related source file is "F:/FPGA/ps2_lcd_1602/LCD1602.vhd".WARNING:Xst:1780 - Signal <m> is never used or assigned.    Found 31x8-bit dual-port distributed RAM for signal <cgram>.    -----------------------------------------------------------------------    | aspect ratio       | 31-word x 8-bit                     |          |    | clock              | connected to signal <key_ready>     | rise     |    | write enable       | connected to internal node          | low      |    | address            | connected to signal <key_cnt>       |          |    | dual address       | connected to signal <cnt1>          |          |    | data in            | connected to signal <ps2_data>      |          |    | data out           | not connected                       |          |    | dual data out      | connected to internal node          |          |    | ram_style          | Auto                                |          |    -----------------------------------------------------------------------INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.    Found finite state machine <FSM_0> for signal <Current_State>.    -----------------------------------------------------------------------    | States             | 7                                              |    | Transitions        | 7                                              |    | Inputs             | 0                                              |    | Outputs            | 7                                              |    | Clock              | LCD_Clk (rising_edge)                          |    | Reset              | Reset (negative)                               |    | Reset type         | asynchronous                                   |    | Reset State        | set_dlnf                                       |    | Power Up State     | set_dlnf                                       |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 8-bit register for signal <LCD_Data>.    Found 1-bit register for signal <LCD_RS>.    Found 5-bit adder for signal <$n0026> created at line 99.    Found 8-bit addsub for signal <$n0027>.    Found 8-bit adder for signal <$n0028> created at line 106.    Found 5-bit comparator less for signal <$n0029> created at line 98.    Found 5-bit comparator lessequal for signal <$n0030> created at line 103.    Found 15-bit comparator less for signal <$n0031> created at line 48.    Found 9-bit comparator less for signal <$n0032> created at line 61.    Found 1-bit register for signal <CLK1>.    Found 1-bit register for signal <Clk_Out>.    Found 5-bit register for signal <cnt1>.    Found 5-bit up counter for signal <key_cnt>.    Found 15-bit up counter for signal <n1>.    Found 9-bit up counter for signal <n2>.    Summary:	inferred   1 Finite State Machine(s).	inferred   1 RAM(s).	inferred   3 Counter(s).	inferred  11 D-type flip-flop(s).	inferred   3 Adder/Subtractor(s).	inferred   4 Comparator(s).Unit <LCD1602> synthesized.Synthesizing Unit <ps2>.    Related source file is "F:/FPGA/ps2_lcd_1602/ps2.vhd".    Found finite state machine <FSM_1> for signal <c_state>.    -----------------------------------------------------------------------    | States             | 4                                              |    | Transitions        | 10                                             |    | Inputs             | 3                                              |    | Outputs            | 4                                              |    | Clock              | clock (rising_edge)                            |    | Reset              | resetn (negative)                              |    | Reset type         | asynchronous                                   |    | Reset State        | idle                                           |    | Power Up State     | idle                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------WARNING:Xst:737 - Found 11-bit latch for signal <hit_cnt>.WARNING:Xst:737 - Found 1-bit latch for signal <hit_1>.    Found 4x1-bit ROM for signal <hit>.    Found 11-bit adder for signal <$n0018> created at line 214.    Found 1-bit xor2 for signal <$n0088> created at line 137.    Found 1-bit register for signal <act_ps2_clk>.    Found 3-bit up counter for signal <cntval>.    Found 1-bit register for signal <err>.    Found 1-bit register for signal <latch>.    Found 8-bit register for signal <leds>.    Found 1-bit register for signal <parbit>.    Found 1-bit register for signal <parset>.    Found 1-bit register for signal <prv_ps2_clk>.    Found 8-bit register for signal <recdata>.    Found 1-bit register for signal <shift>.    Summary:	inferred   1 Finite State Machine(s).