inferred   1 ROM(s).	inferred   1 Counter(s).	inferred  23 D-type flip-flop(s).	inferred   1 Adder/Subtractor(s).Unit <ps2> synthesized.Synthesizing Unit <ps2_lcd1602_1>.    Related source file is "F:/FPGA/ps2_lcd_1602/ps2_lcd1602_1.vhd".Unit <ps2_lcd1602_1> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================HDL Synthesis ReportMacro Statistics# LUT RAMs                                             : 1 31x8-bit dual-port distributed RAM                    : 1# ROMs                                                 : 1 4x1-bit ROM                                           : 1# Adders/Subtractors                                   : 4 11-bit adder                                          : 1 5-bit adder                                           : 1 8-bit adder                                           : 1 8-bit addsub                                          : 1# Counters                                             : 3 15-bit up counter                                     : 1 3-bit up counter                                      : 1 5-bit up counter                                      : 1# Registers                                            : 13 1-bit register                                        : 9 5-bit register                                        : 1 8-bit register                                        : 3# Latches                                              : 2 1-bit latch                                           : 1 11-bit latch                                          : 1# Comparators                                          : 3 15-bit comparator less                                : 1 5-bit comparator less                                 : 1 5-bit comparator lessequal                            : 1# Xors                                                 : 1 1-bit xor2                                            : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <a0/c_state> on signal <c_state[1:2]> with sequential encoding.-------------------- State  | Encoding-------------------- idle   | 00 start  | 01 data   | 10 parity | 11--------------------Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <a1/Current_State> on signal <Current_State[1:3]> with gray encoding.---------------------------- State          | Encoding---------------------------- set_dlnf       | 000 set_cursor     | 001 set_dcb        | 011 set_cgram      | 010 write_cgram    | 110 set_ddram      | 111 write_lcd_data | 101----------------------------=========================================================================Advanced HDL Synthesis ReportMacro Statistics# FSMs                                                 : 2# LUT RAMs                                             : 1 31x8-bit dual-port distributed RAM                    : 1# ROMs                                                 : 1 4x1-bit ROM                                           : 1# Adders/Subtractors                                   : 4 11-bit adder                                          : 1 5-bit adder                                           : 1 8-bit adder                                           : 1 8-bit addsub                                          : 1# Counters                                             : 3 15-bit up counter                                     : 1 3-bit up counter                                      : 1 5-bit up counter                                      : 1# Registers                                            : 43 Flip-Flops                                            : 43# Latches                                              : 2 1-bit latch                                           : 1 11-bit latch                                          : 1# Comparators                                          : 3 15-bit comparator less                                : 1 5-bit comparator less                                 : 1 5-bit comparator lessequal                            : 1# Xors                                                 : 1 1-bit xor2                                            : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx.Optimizing unit <ps2_lcd1602_1> ...Optimizing unit <LCD1602> ...Optimizing unit <ps2> ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block ps2_lcd1602_1, actual ratio is 4.FlipFlop a1/Current_State_FFd1 has been replicated 1 time(s)FlipFlop a1/cnt1_0 has been replicated 2 time(s)FlipFlop a1/cnt1_1 has been replicated 2 time(s)FlipFlop a1/cnt1_2 has been replicated 2 time(s)FlipFlop a1/cnt1_3 has been replicated 3 time(s)FlipFlop a1/cnt1_4 has been replicated 2 time(s)=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : ps2_lcd1602_1.ngrTop Level Output File Name         : ps2_lcd1602_1Output Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 16Cell Usage :# BELS                             : 276#      GND                         : 1#      INV                         : 9#      LUT1                        : 16#      LUT2                        : 33#      LUT2_D                      : 3#      LUT3                        : 28#      LUT3_D                      : 2#      LUT3_L                      : 13#      LUT4                        : 85#      LUT4_D                      : 6#      LUT4_L                      : 16#      MUXCY                       : 27#      MUXF5                       : 15#      VCC                         : 1#      XORCY                       : 21# FlipFlops/Latches                : 90#      FDC                         : 13#      FDCE                        : 11#      FDE                         : 9#      FDP                         : 16#      FDPE                        : 9#      FDR                         : 20#      LD                          : 11#      LDC                         : 1# RAMS                             : 16#      RAM16X1D                    : 16# Clock Buffers                    : 3#      BUFG                        : 2#      BUFGP                       : 1# IO Buffers                       : 15#      IBUF                        : 4#      OBUF                        : 11=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5  Number of Slices:                     129  out of   3584     3%   Number of Slice Flip Flops:            90  out of   7168     1%   Number of 4 input LUTs:               234  out of   7168     3%      Number used as logic: 202    Number used as RAMs: 32 Number of bonded IOBs:                 16  out of    141    11%   Number of GCLKs:                        3  out of      8    37%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+CLK                                | BUFGP                  | 44    |a1/Clk_Out1                        | BUFG                   | 29    |a0/hit_11                          | BUFG                   | 21    |a0/_n0017(a0/_n00171:O)            | NONE(*)(a0/hit_1)      | 1     |a0/N3(a0/Mrom_data_Mrom_hit:O)     | NONE(*)(a0/hit_cnt_8)  | 11    |-----------------------------------+------------------------+-------+(*) These 2 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary: