?? ps2_lcd1602_1.drc
字號:
WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/_n0017 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/N3 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.DRC detected 0 errors and 2 warnings.
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