?? ps2_lcd1602_1.drc
字號:
WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/_n0017 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/N3 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.DRC detected 0 errors and 2 warnings.?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -