Release 8.1i Map I.24Xilinx Mapping Report File for Design 'ps2_lcd1602_1'Design Information------------------Command Line   : C:\Xilinx\bin\nt\map.exe -ise
F:/FPGA/ps2_lcd_1602/ps2_lcd_1602.ise -intstyle ise -p xc3s400-pq208-5 -cm area
-pr b -k 4 -c 100 -o ps2_lcd1602_1_map.ncd ps2_lcd1602_1.ngd ps2_lcd1602_1.pcf Target Device  : xc3s400Target Package : pq208Target Speed   : -5Mapper Version : spartan3 -- $Revision: 1.34 $Mapped Date    : Thu May 17 22:17:15 2007Design Summary--------------Number of errors:      0Number of warnings:    5Logic Utilization:  Total Number Slice Registers:        79 out of   7,168    1%    Number used as Flip Flops:                    67    Number used as Latches:                       12  Number of 4 input LUTs:             187 out of   7,168    2%Logic Distribution:  Number of occupied Slices:                          142 out of   3,584    3%    Number of Slices containing only related logic:     142 out of     142  100%    Number of Slices containing unrelated logic:          0 out of     142    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:            235 out of   7,168    3%  Number used as logic:                187  Number used as a route-thru:          16  Number used for Dual Port RAMs:       32    (Two LUTs used per Dual Port RAM)  Number of bonded IOBs:               16 out of     141   11%    IOB Flip Flops:                    11  Number of GCLKs:                     3 out of       8   37%Total equivalent gate count for design:  4,049Additional JTAG gate count for IOBs:  768Peak Memory Usage:  136 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network a1/inst_Mram_mem16/SPO has no load.WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 15
   more times for the following (max. 5 shown):   a1/inst_Mram_mem17/SPO,   a1/inst_Mram_mem21/SPO,   a1/inst_Mram_mem31/SPO,   a1/inst_Mram_mem41/SPO,   a1/inst_Mram_mem51/SPO   To see the details of these warning messages, please use the -detail switch.WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_a1/Clk_Out/a1/Clk_Out_BUFG" (output signal=a1/Clk_Out)
   has a mix of clock and non-clock loads. The non-clock loads are:   Pin D of a1/Clk_OutWARNING:PhysDesignRules:372 - Gated clock. Clock net a0/_n0017 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/N3 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "CLK_BUFGP" (output signal=CLK_BUFGP),   BUFG symbol "a0/hit_1_BUFG" (output signal=a0/hit_1),   BUFG symbol "a1/Clk_Out_BUFG" (output signal=a1/Clk_Out)INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| CLK                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || LCD_Data<0>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<1>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<2>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<3>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<4>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<5>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<6>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_Data<7>                        | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_EN                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || LCD_RS                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       || LCD_RW                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || Reset2                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || ps2_clk                            | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   || ps2_dta                            | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   || reset1                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 16Number of Equivalent Gates for Design = 4,049Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 0GCLKs = 3ICAPs = 018X18 Multipliers = 0Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 40IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 10IOB Flip Flops = 11Unbonded IOBs = 0Bonded IOBs = 16XORs = 21CARRY_INITs = 15CARRY_SKIPs = 0CARRY_MUXes = 26Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 16MUXFs = 15MULT_ANDs = 04 input LUTs used as Route-Thrus = 164 input LUTs = 187Slice Latches not driven by LUTs = 12Slice Latches = 12Slice Flip Flops not driven by LUTs = 29Slice Flip Flops = 67SliceMs = 16SliceLs = 126Slices = 142F6 Muxes = 0F5 Muxes = 15F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 4Number of LUT signals with 3 loads = 10Number of LUT signals with 2 loads = 28Number of LUT signals with 1 load = 139NGM Average fanout of LUT = 1.53NGM Maximum fanout of LUT = 11NGM Average fanin for LUT = 3.3690Number of LUT symbols = 187