library IEEE;
use IEEE.std_logic_1164.all;
entity hong_lv is
    port (
        scan_in:in STD_LOGIC_VECTOR (7 downto 0);
        hong_out: out STD_LOGIC_VECTOR (7 downto 0);
        lv_out: out STD_LOGIC_VECTOR (7 downto 0));
end hong_lv;


architecture hong_lv_arch of hong_lv is
begin
process(scan_in)
begin
      hong_out<=scan_in;
      lv_out <=scan_in;
end process;
end hong_lv_arch;