Release 6.3i Map G.35Xilinx Mapping Report File for Design 'dianzheng'Design Information------------------Command Line   : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s50-tq144-6 -cm
area -pr b -k 4 -c 100 -tx off -o dianzheng_map.ncd dianzheng.ngd dianzheng.pcf Target Device  : x2s50Target Package : tq144Target Speed   : -6Mapper Version : spartan2 -- $Revision: 1.16.8.2 $Mapped Date    : Wed Apr 11 12:28:09 2007Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:        64 out of  1,536    4%  Number of 4 input LUTs:            54 out of  1,536    3%Logic Distribution:    Number of occupied Slices:                          62 out of    768    8%    Number of Slices containing only related logic:     62 out of     62  100%    Number of Slices containing unrelated logic:         0 out of     62    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          106 out of  1,536    6%      Number used as logic:                        54      Number used as a route-thru:                 52   Number of bonded IOBs:            24 out of     92   26%   Number of Tbufs:                   1 out of    832    1%   Number of GCLKs:                   1 out of      4   25%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  1,193Additional JTAG gate count for IOBs:  1,200Peak Memory Usage:  57 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || hong<0>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<1>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<2>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<3>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<4>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<5>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<6>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hong<7>                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || lu<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<0>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<1>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<2>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<3>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<4>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<5>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<6>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || y<7>                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 25Number of Equivalent Gates for Design = 1,193Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 1Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 50IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 24Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 74 input LUTs used as Route-Thrus = 524 input LUTs = 54Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 50Slice Flip Flops = 64Slices = 62Number of LUT signals with 4 loads = 1Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 5Number of LUT signals with 1 load = 47NGM Average fanout of LUT = 1.41NGM Maximum fanout of LUT = 15NGM Average fanin for LUT = 3.0741Number of LUT symbols = 54Number of IPAD symbols = 1