library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cnta is
    Port ( clk : in std_logic;
           q : out std_logic_vector(2 downto 0));
end cnta;

architecture Behavioral of cnta is

begin
   process(clk)
   variable tmp:std_logic_vector(2 downto 0);
   begin
      if clk'event and clk='1'then
	    tmp:=tmp+1;
	 end if;
	   q<=tmp-1;
   end process;
end Behavioral;