--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : dianzheng.vhf
-- /___/   /\     Timestamp : 04/11/2007 12:27:58
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: dianzheng
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity dianzheng is
   port ( clk  : in    std_logic; 
          hong : out   std_logic_vector (7 downto 0); 
          lu   : out   std_logic_vector (7 downto 0); 
          y    : out   std_logic_vector (7 downto 0));
end dianzheng;

architecture BEHAVIORAL of dianzheng is
   signal XLXN_1  : std_logic_vector (1 downto 0);
   signal XLXN_5  : std_logic;
   signal XLXN_11 : std_logic_vector (2 downto 0);
   signal XLXN_14 : std_logic_vector (7 downto 0);
   component chw
      port ( clk : in    std_logic; 
             q   : out   std_logic_vector (1 downto 0));
   end component;
   
   component cnta
      port ( clk : in    std_logic; 
             q   : out   std_logic_vector (2 downto 0));
   end component;
   
   component cont
      port ( ch  : in    std_logic_vector (1 downto 0); 
             sel : in    std_logic_vector (2 downto 0); 
             q   : out   std_logic_vector (7 downto 0));
   end component;
   
   component dz_scan
      port ( lie : out   std_logic_vector (7 downto 0); 
             clk : in    std_logic; 
             sel : in    std_logic_vector (2 downto 0));
   end component;
   
   component hong_lv
      port ( scan_in  : in    std_logic_vector (7 downto 0); 
             hong_out : out   std_logic_vector (7 downto 0); 
             lv_out   : out   std_logic_vector (7 downto 0));
   end component;
   
   component fpq2ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
begin
   XLXI_1 : chw
      port map (clk=>XLXN_5,      
                q(1 downto 0)=>XLXN_1(1 downto 0));
   
   XLXI_2 : cnta
      port map (clk=>XLXN_5,      
                q(2 downto 0)=>XLXN_11(2 downto 0));
   
   XLXI_3 : cont
      port map (ch(1 downto 0)=>XLXN_1(1 downto 0),      
                sel(2 downto 0)=>XLXN_11(2 downto 0),      
                q(7 downto 0)=>y(7 downto 0));
   
   XLXI_9 : dz_scan
      port map (clk=>XLXN_5,      
                sel(2 downto 0)=>XLXN_11(2 downto 0),      
                lie(7 downto 0)=>XLXN_14(7 downto 0));
   
   XLXI_10 : hong_lv
      port map (scan_in(7 downto 0)=>XLXN_14(7 downto 0),      
                hong_out(7 downto 0)=>hong(7 downto 0),      
                lv_out(7 downto 0)=>lu(7 downto 0));
   
   XLXI_12 : fpq2ms
      port map (CLK=>clk,      
                CP=>XLXN_5);
   
end BEHAVIORAL;