Release 6.3i Par G.38Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.ST23::  Wed Apr 11 12:28:11 2007D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 dianzheng_map.ncd
dianzheng.ncd dianzheng.pcf Constraints file: dianzheng.pcfLoading device database for application Par from file "dianzheng_map.ncd".   "dianzheng" is an NCD, version 2.38, device xc2s50, package tq144, speed -6Loading device for application Par from file 'v50.nph' in environment D:/Xilinx.Device speed data version:  PRODUCTION 1.27 2004-06-25.Resolved that GCLKIOB <clk> must be placed at site P88.Resolved that IOB <lu<0>> must be placed at site P132.Resolved that IOB <lu<1>> must be placed at site P133.Resolved that IOB <lu<2>> must be placed at site P134.Resolved that IOB <lu<3>> must be placed at site P136.Resolved that IOB <lu<4>> must be placed at site P137.Resolved that IOB <lu<5>> must be placed at site P138.Resolved that IOB <lu<6>> must be placed at site P139.Resolved that IOB <lu<7>> must be placed at site P140.Resolved that IOB <y<0>> must be placed at site P84.Resolved that IOB <y<1>> must be placed at site P86.Resolved that IOB <y<2>> must be placed at site P87.Resolved that IOB <y<3>> must be placed at site P94.Resolved that IOB <hong<0>> must be placed at site P113.Resolved that IOB <y<4>> must be placed at site P95.Resolved that IOB <hong<1>> must be placed at site P115.Resolved that IOB <y<5>> must be placed at site P99.Resolved that IOB <hong<2>> must be placed at site P117.Resolved that IOB <y<6>> must be placed at site P101.Resolved that IOB <hong<3>> must be placed at site P120.Resolved that IOB <y<7>> must be placed at site P103.Resolved that IOB <hong<4>> must be placed at site P122.Resolved that IOB <hong<5>> must be placed at site P124.Resolved that IOB <hong<6>> must be placed at site P126.Resolved that IOB <hong<7>> must be placed at site P130.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            24 out of 92     26%      Number of LOCed External IOBs   24 out of 24    100%   Number of SLICEs                   62 out of 768     8%   Number of GCLKs                     1 out of 4      25%   Number of TBUFs                     1 out of 832     1%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9898d7) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8..Phase 5.8 (Checksum:99c0bd) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file dianzheng.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 375 unrouted;       REAL time: 0 secs Phase 2: 347 unrouted;       REAL time: 5 secs Phase 3: 56 unrouted;       REAL time: 5 secs Phase 4: 0 unrouted;       REAL time: 5 secs Total REAL time to Router completion: 5 secs Total CPU time to Router completion: 4 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+|         clk_BUFGP          |  Global  |   10   |  0.072     |  0.462      |+----------------------------+----------+--------+------------+-------------+|            XLXN_5          |   Local  |   27   |  1.631     |  3.802      |+----------------------------+----------+--------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 165The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        1.283   The MAXIMUM PIN DELAY IS:                               3.802   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.831   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------         161         172          27          15           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 4 secs Peak Memory Usage:  48 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file dianzheng.ncd.PAR done.