# Xilinx CORE Generator 6.3i
# User = student32
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\zsx\dianzheng\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\zsx\dianzheng
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\zsx\dianzheng
SETPROJECT .
Set current Project to E:\zsx\dianzheng
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1060
XIPCPJSENDCORES spartan2