Release 6.2i - xst G.28Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.64 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.64 s | Elapsed : 0.00 / 1.00 s --> Reading design: pingche.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : pingche.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : pingcheOutput Format                      : NGCTarget Device                      : xc2s50-6-tq144---- Source OptionsTop Module Name                    : pingcheAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : pingche.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NOtristate2logic                     : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/VHDL/past/pingche/jsq1.vhdl in Library work.Architecture behavioral of Entity jsq1 is up to date.Compiling vhdl file E:/VHDL/past/pingche/jsq2.vhdl in Library work.Architecture behavioral of Entity jsq2 is up to date.Compiling vhdl file E:/VHDL/past/pingche/jsq3.vhdl in Library work.Architecture behavioral of Entity jsq3 is up to date.Compiling vhdl file E:/VHDL/past/pingche/jsq4.vhdl in Library work.Architecture behavioral of Entity jsq4 is up to date.Compiling vhdl file E:/VHDL/past/pingche/jsq5.vhdl in Library work.Architecture behavioral of Entity jsq5 is up to date.Compiling vhdl file E:/VHDL/past/pingche/jsq6.vhdl in Library work.Architecture behavioral of Entity jsq6 is up to date.Compiling vhdl file E:/VHDL/past/pingche/fpq1s.vhdl in Library work.Architecture behavioral of Entity fpq1s is up to date.Compiling vhdl file E:/VHDL/past/pingche/fpq2ms.vhdl in Library work.Architecture behavioral of Entity fpq2ms is up to date.Compiling vhdl file E:/VHDL/past/pingche/jsq.vhf in Library work.Architecture behavioral of Entity jsq is up to date.Compiling vhdl file E:/VHDL/past/pingche/s_6.vhdl in Library work.Architecture behavioral of Entity s_6 is up to date.Compiling vhdl file E:/VHDL/past/pingche/scq.vhdl in Library work.Architecture behavioral of Entity scq is up to date.Compiling vhdl file E:/VHDL/past/pingche/xzq.vhdl in Library work.Architecture behavioral of Entity szq is up to date.Compiling vhdl file E:/VHDL/past/pingche/ymq.vhdl in Library work.Architecture behavioral of Entity ymq is up to date.Compiling vhdl file E:/VHDL/past/pingche/kz2.vhdl in Library work.Architecture behavioral of Entity kz2 is up to date.Compiling vhdl file E:/VHDL/past/pingche/f5p.vhdl in Library work.Entity <div5freq> (Architecture <behav>) compiled.Compiling vhdl file E:/VHDL/past/pingche/pingche.vhf in Library work.Entity <pingche> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <pingche> (Architecture <behavioral>).Entity <pingche> analyzed. Unit <pingche> generated.Analyzing Entity <fpq1s> (Architecture <behavioral>).Entity <fpq1s> analyzed. Unit <fpq1s> generated.Analyzing Entity <fpq2ms> (Architecture <behavioral>).Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.Analyzing Entity <jsq> (Architecture <behavioral>).Entity <jsq> analyzed. Unit <jsq> generated.Analyzing Entity <jsq1> (Architecture <behavioral>).Entity <jsq1> analyzed. Unit <jsq1> generated.Analyzing Entity <jsq2> (Architecture <behavioral>).Entity <jsq2> analyzed. Unit <jsq2> generated.Analyzing Entity <jsq3> (Architecture <behavioral>).Entity <jsq3> analyzed. Unit <jsq3> generated.Analyzing Entity <jsq4> (Architecture <behavioral>).Entity <jsq4> analyzed. Unit <jsq4> generated.Analyzing Entity <jsq5> (Architecture <behavioral>).Entity <jsq5> analyzed. Unit <jsq5> generated.Analyzing Entity <jsq6> (Architecture <behavioral>).Entity <jsq6> analyzed. Unit <jsq6> generated.Analyzing Entity <s_6> (Architecture <behavioral>).Entity <s_6> analyzed. Unit <s_6> generated.Analyzing Entity <scq> (Architecture <behavioral>).Entity <scq> analyzed. Unit <scq> generated.Analyzing Entity <szq> (Architecture <behavioral>).WARNING:Xst:819 - E:/VHDL/past/pingche/xzq.vhdl line 24: The following signals are missing in the process sensitivity list:   Q6, Q5, Q4, Q3, Q2, Q1.Entity <szq> analyzed. Unit <szq> generated.Analyzing Entity <ymq> (Architecture <behavioral>).Entity <ymq> analyzed. Unit <ymq> generated.Analyzing Entity <kz2> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <b> in unit <kz2> never changes during circuit operation. The register is replaced by logic.Entity <kz2> analyzed. Unit <kz2> generated.Analyzing Entity <div5freq> (Architecture <behav>).WARNING:Xst:819 - E:/VHDL/past/pingche/f5p.vhdl line 23: The following signals are missing in the process sensitivity list:   clktmp.WARNING:Xst:819 - E:/VHDL/past/pingche/f5p.vhdl line 63: The following signals are missing in the process sensitivity list:   clktmp3.Entity <div5freq> analyzed. Unit <div5freq> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <jsq6>.    Related source file is E:/VHDL/past/pingche/jsq6.vhdl.    Found 4-bit up counter for signal <D6>.    Summary:	inferred   1 Counter(s).Unit <jsq6> synthesized.Synthesizing Unit <jsq5>.    Related source file is E:/VHDL/past/pingche/jsq5.vhdl.    Found 4-bit up counter for signal <D5>.    Found 1-bit register for signal <COUT>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <jsq5> synthesized.Synthesizing Unit <jsq4>.    Related source file is E:/VHDL/past/pingche/jsq4.vhdl.    Found 4-bit up counter for signal <D4>.    Found 1-bit register for signal <COUT>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <jsq4> synthesized.Synthesizing Unit <jsq3>.    Related source file is E:/VHDL/past/pingche/jsq3.vhdl.    Found 4-bit up counter for signal <D3>.    Found 1-bit register for signal <COUT>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <jsq3> synthesized.Synthesizing Unit <jsq2>.    Related source file is E:/VHDL/past/pingche/jsq2.vhdl.    Found 4-bit up counter for signal <D2>.    Found 1-bit register for signal <COUT>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <jsq2> synthesized.Synthesizing Unit <jsq1>.    Related source file is E:/VHDL/past/pingche/jsq1.vhdl.    Found 4-bit up counter for signal <D1>.    Found 1-bit register for signal <COUT>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <jsq1> synthesized.Synthesizing Unit <div5freq>.    Related source file is E:/VHDL/past/pingche/f5p.vhdl.    Found 1-bit register for signal <clktmp>.    Found 1-bit register for signal <clktmp2>.    Found 1-bit register for signal <clktmp3>.    Found 3-bit up counter for signal <cnt>.    Found 3-bit up counter for signal <cnt2>.    Found 3 1-bit 2-to-1 multiplexers.    Summary:	inferred   2 Counter(s).	inferred   3 D-type flip-flop(s).	inferred   3 Multiplexer(s).Unit <div5freq> synthesized.Synthesizing Unit <kz2>.    Related source file is E:/VHDL/past/pingche/kz2.vhdl.    Using one-hot encoding for signal <a>.    Found 1-bit register for signal <COUNT_CLR>.    Found 1-bit tristate buffer for signal <COUNT_LOAD>.    Found 1-bit tristate buffer for signal <COUNT_EN>.    Found 2-bit register for signal <a>.    Found 1-bit register for signal <Mtridata_COUNT_EN> created at line 27.