library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity YIWEI is
  port(EN:in std_logic;
       clk:in std_logic;
	  clr:in std_logic;
	  rstcode:in std_logic;
	  comp:in std_logic;
       d:in std_logic_vector(3 downto 0);
	  s:buffer std_logic;
	  q:buffer std_logic;
	  K1,K2,K3,K4: buffer std_logic_vector(3 downto 0);
	  K5,K6,K7,K8: buffer std_logic_vector(3 downto 0));
end YIWEI;

architecture Behavioral of YIWEI is
TYPE CNT IS ARRAY(8 DOWNTO 1) OF STD_LOGIC_VECTOR(3 DOWNTO 0);  
SIGNAL COUNT: CNT; 
type value is array (8 downto 1)  of std_logic_vector(3 downto 0) ;
signal a,b:value;
begin
  process(EN,clk)
  begin
   if clr='1' then
    	     COUNT(1)<="1111";
          COUNT(2)<="1111";
          COUNT(3)<="1111";
          COUNT(4)<="1111";
          COUNT(5)<="1111";
          COUNT(6)<="1111";
          COUNT(7)<="1111";
          COUNT(8)<="1111";
     elsif clk='1' AND clk'EVENT and en='1' then
	   COUNT(8 DOWNTO 2)<=COUNT(7 DOWNTO 1);
	   COUNT(1)<=D;
     END IF;
  K1<=COUNT(1);
  K2<=COUNT(2);
  K3<=COUNT(3);
  K4<=COUNT(4);
  K5<=COUNT(5);
  K6<=COUNT(6);
  K7<=COUNT(7);
  K8<=COUNT(8);
  end process;
  
  process(comp) 
  begin
   if  comp='0'  then
	    b(1)<=k1;
	    b(2)<=k2;
	    b(3)<=k3;
	    b(4)<=k4;
	    b(5)<=k5;
	    b(6)<=k6;
	    b(7)<=k7;
	    b(8)<=k8;
    end if;
  end process;

  process(rstcode)
  begin
	 if rstcode='0' and q='0' then
	    a(1)<=k1;
	    a(2)<=k2;
	    a(3)<=k3;
	    a(4)<=k4;
	    a(5)<=k5;
	    a(6)<=k6;
	    a(7)<=k7;
	    a(8)<=k8;
	 end if;
   end process;
   
   process(a,b,clk)
   begin
     if clk'event and clk='1' then
	       if a=b then
		     q<='0';s<='1';
	       else
	          q<='1';s<='0';
		  end if;
	end if;
   end process;

end Behavioral;