library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY YMQ IS
  PORT  (
         A: IN std_logic_vector(3 downto 0);
         Q:OUT std_logic_vector(6 downto 0)
	    );
END YMQ;
ARCHITECTURE Behavioral OF YMQ IS		--- '0'you  xiao
BEGIN 
   PROCESS(A)
   BEGIN 
      CASE A IS
          WHEN"0000"=>Q<="1000000";   --0 
          WHEN"0001"=>Q<="1111001";   --1
          WHEN"0010"=>Q<="0100100";   --2
          WHEN"0011"=>Q<="0110000";   --3
          WHEN"0100"=>Q<="0011001";   --4
          WHEN"0101"=>Q<="0010010";   --5
          WHEN"0110"=>Q<="0000010";   --6
          WHEN"0111"=>Q<="1111000";   --7
          WHEN"1000"=>Q<="0000000";   --8
          WHEN"1001"=>Q<="0010000";   --9
		WHEN"1111"=>Q<="1111111";
          WHEN  OTHERS =>Q<="1111111";   
      END CASE;
   END PROCESS;
END  Behavioral;