Release 6.2i - xst G.28Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.89 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.89 s | Elapsed : 0.00 / 1.00 s --> Reading design: mimasuo.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : mimasuo.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : mimasuoOutput Format                      : NGCTarget Device                      : xc2s50-6-tq144---- Source OptionsTop Module Name                    : mimasuoAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : mimasuo.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NOtristate2logic                     : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file E:/mimasuo/fpq10ms.vhdl in Library work.Architecture behavioral of Entity fpq10ms is up to date.Compiling vhdl file E:/mimasuo/key.vhdl in Library work.Architecture behavioral of Entity keyval is up to date.Compiling vhdl file E:/mimasuo/SE8.vhdl in Library work.Architecture behavioral of Entity se8 is up to date.Compiling vhdl file E:/mimasuo/xzq81.vhdl in Library work.Architecture behavioral of Entity xzq81 is up to date.Compiling vhdl file E:/mimasuo/yiwei.vhdl in Library work.Architecture behavioral of Entity yiwei is up to date.Compiling vhdl file E:/mimasuo/fpq01ms.vhdl in Library work.Architecture behavioral of Entity fpq01ms is up to date.Compiling vhdl file E:/mimasuo/ymq.vhdl in Library work.Architecture behavioral of Entity ymq is up to date.Compiling vhdl file E:/mimasuo/mimasuo.vhf in Library work.Entity <mimasuo> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <mimasuo> (Architecture <behavioral>).INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 18: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 19: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 20: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/mimasuo/mimasuo.vhf line 21: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <mimasuo> analyzed. Unit <mimasuo> generated.Analyzing Entity <fpq10ms> (Architecture <behavioral>).Entity <fpq10ms> analyzed. Unit <fpq10ms> generated.Analyzing Entity <keyval> (Architecture <behavioral>).Entity <keyval> analyzed. Unit <keyval> generated.Analyzing Entity <se8> (Architecture <behavioral>).Entity <se8> analyzed. Unit <se8> generated.Analyzing Entity <xzq81> (Architecture <behavioral>).WARNING:Xst:819 - E:/mimasuo/xzq81.vhdl line 28: The following signals are missing in the process sensitivity list:   Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1.Entity <xzq81> analyzed. Unit <xzq81> generated.Analyzing Entity <yiwei> (Architecture <behavioral>).WARNING:Xst:819 - E:/mimasuo/yiwei.vhdl line 30: The following signals are missing in the process sensitivity list:   clr, COUNT.WARNING:Xst:819 - E:/mimasuo/yiwei.vhdl line 55: The following signals are missing in the process sensitivity list:   K1, K2, K3, K4, K5, K6, K7, K8.WARNING:Xst:819 - E:/mimasuo/yiwei.vhdl line 69: The following signals are missing in the process sensitivity list:   q, K1, K2, K3, K4, K5, K6, K7, K8.Entity <yiwei> analyzed. Unit <yiwei> generated.Analyzing Entity <fpq01ms> (Architecture <behavioral>).Entity <fpq01ms> analyzed. Unit <fpq01ms> generated.Analyzing Entity <ymq> (Architecture <behavioral>).Entity <ymq> analyzed. Unit <ymq> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <ymq>.    Related source file is E:/mimasuo/ymq.vhdl.    Found 16x7-bit ROM for signal <Q>.    Summary:	inferred   1 ROM(s).Unit <ymq> synthesized.Synthesizing Unit <fpq01ms>.    Related source file is E:/mimasuo/fpq01ms.vhdl.    Found 1-bit tristate buffer for signal <CP>.    Found 12-bit comparator lessequal for signal <$n0002>.    Found 12-bit comparator greatequal for signal <$n0007>.    Found 12-bit comparator lessequal for signal <$n0008>.    Found 12-bit up counter for signal <a>.    Found 1-bit register for signal <Mtridata_CP> created at line 28.    Found 1-bit register for signal <Mtrien_CP> created at line 28.    Summary:	inferred   1 Counter(s).	inferred   2 D-type flip-flop(s).	inferred   3 Comparator(s).	inferred   1 Tristate(s).Unit <fpq01ms> synthesized.Synthesizing Unit <yiwei>.    Related source file is E:/mimasuo/yiwei.vhdl.WARNING:Xst:737 - Found 4-bit latch for signal <b_1>.WARNING:Xst:737 - Found 4-bit latch for signal <b_2>.WARNING:Xst:737 - Found 4-bit latch for signal <b_3>.WARNING:Xst:737 - Found 4-bit latch for signal <b_4>.WARNING:Xst:737 - Found 4-bit latch for signal <b_5>.WARNING:Xst:737 - Found 4-bit latch for signal <b_6>.WARNING:Xst:737 - Found 4-bit latch for signal <b_7>.WARNING:Xst:737 - Found 4-bit latch for signal <b_8>.WARNING:Xst:737 - Found 4-bit latch for signal <a_1>.WARNING:Xst:737 - Found 4-bit latch for signal <a_2>.WARNING:Xst:737 - Found 4-bit latch for signal <a_3>.WARNING:Xst:737 - Found 4-bit latch for signal <a_4>.WARNING:Xst:737 - Found 4-bit latch for signal <a_5>.WARNING:Xst:737 - Found 4-bit latch for signal <a_6>.WARNING:Xst:737 - Found 4-bit latch for signal <a_7>.WARNING:Xst:737 - Found 4-bit latch for signal <a_8>.    Found 1-bit register for signal <q>.    Found 1-bit register for signal <s>.    Found 4-bit comparator equal for signal <$n0003>.    Found 4-bit comparator equal for signal <$n0004>.    Found 4-bit comparator equal for signal <$n0005>.    Found 4-bit comparator equal for signal <$n0006>.    Found 4-bit comparator equal for signal <$n0007>.    Found 4-bit comparator equal for signal <$n0008>.    Found 4-bit comparator equal for signal <$n0009>.    Found 4-bit comparator equal for signal <$n0010>.    Found 32-bit register for signal <COUNT>.    Summary:	inferred  34 D-type flip-flop(s).	inferred   8 Comparator(s).Unit <yiwei> synthesized.Synthesizing Unit <xzq81>.    Related source file is E:/mimasuo/xzq81.vhdl.    Found 4-bit 8-to-1 multiplexer for signal <Q>.    Summary:	inferred   4 Multiplexer(s).Unit <xzq81> synthesized.Synthesizing Unit <se8>.    Related source file is E:/mimasuo/SE8.vhdl.    Found 3-bit up counter for signal <i>.    Summary:	inferred   1 Counter(s).Unit <se8> synthesized.Synthesizing Unit <keyval>.    Related source file is E:/mimasuo/key.vhdl.    Found 4-bit register for signal <value>.    Found 1-bit register for signal <comp>.    Found 1-bit register for signal <rstcode>.    Found 1-bit register for signal <pressed>.    Found 1-bit register for signal <clr_out>.    Found 4-bit register for signal <keydrv>.    Found 4-bit up counter for signal <dd>.    Found 1-bit register for signal <tpressed>.    Summary:	inferred   1 Counter(s).	inferred  13 D-type flip-flop(s).Unit <keyval> synthesized.Synthesizing Unit <fpq10ms>.    Related source file is E:/mimasuo/fpq10ms.vhdl.    Found 1-bit tristate buffer for signal <CP>.    Found 19-bit comparator lessequal for signal <$n0002>.    Found 19-bit comparator greatequal for signal <$n0007>.    Found 19-bit comparator lessequal for signal <$n0008>.    Found 19-bit up counter for signal <a>.    Found 1-bit register for signal <Mtridata_CP> created at line 28.    Found 1-bit register for signal <Mtrien_CP> created at line 28.    Summary:	inferred   1 Counter(s).	inferred   2 D-type flip-flop(s).	inferred   3 Comparator(s).	inferred   1 Tristate(s).Unit <fpq10ms> synthesized.Synthesizing Unit <mimasuo>.    Related source file is E:/mimasuo/mimasuo.vhf.Unit <mimasuo> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                             : 1 16x7-bit ROM                      : 1# Counters                         : 4 19-bit up counter                 : 1 4-bit up counter                  : 1