12-bit up counter                 : 1 3-bit up counter                  : 1# Registers                        : 21 1-bit register                    : 11 4-bit register                    : 10# Latches                          : 16 4-bit latch                       : 16# Comparators                      : 14 19-bit comparator lessequal       : 2 19-bit comparator greatequal      : 1 4-bit comparator equal            : 8 12-bit comparator lessequal       : 2 12-bit comparator greatequal      : 1# Multiplexers                     : 1 4-bit 8-to-1 multiplexer          : 1# Tristates                        : 2 1-bit tristate buffer             : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.Optimizing unit <mimasuo> ...Optimizing unit <xzq81> ...Optimizing unit <fpq10ms> ...Optimizing unit <keyval> ...Optimizing unit <yiwei> ...Optimizing unit <fpq01ms> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block mimasuo, actual ratio is 21.FlipFlop XLXI_5_q has been replicated 1 time(s) to handle iob=true attribute.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : mimasuo.ngrTop Level Output File Name         : mimasuoOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 26Macro Statistics :# ROMs                             : 1#      16x7-bit ROM                : 1# Registers                        : 25#      1-bit register              : 11#      19-bit register             : 4#      4-bit register              : 10# Multiplexers                     : 1#      4-bit 8-to-1 multiplexer    : 1# Tristates                        : 2#      1-bit tristate buffer       : 2# Adders/Subtractors               : 4#      19-bit adder                : 4# Comparators                      : 14#      12-bit comparator greatequal: 1#      12-bit comparator lessequal : 2#      19-bit comparator greatequal: 1#      19-bit comparator lessequal : 2#      4-bit comparator equal      : 8Cell Usage :# BELS                             : 320#      GND                         : 1#      LUT1                        : 45#      LUT1_L                      : 12#      LUT2                        : 21#      LUT2_L                      : 5#      LUT3                        : 37#      LUT3_D                      : 2#      LUT4                        : 59#      LUT4_D                      : 6#      LUT4_L                      : 13#      MUXCY                       : 74#      MUXF5                       : 8#      MUXF6                       : 4#      VCC                         : 1#      XORCY                       : 32# FlipFlops/Latches                : 154#      FD                          : 6#      FDPE                        : 32#      FDR                         : 36#      FDRE                        : 5#      FDS                         : 11#      LD_1                        : 32#      LDE_1                       : 32# Tri-States                       : 2#      BUFT                        : 2# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 25#      IBUF                        : 4#      OBUF                        : 21=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6  Number of Slices:                     153  out of    768    19%   Number of Slice Flip Flops:           154  out of   1536    10%   Number of 4 input LUTs:               200  out of   1536    13%   Number of bonded IOBs:                 25  out of     96    26%   Number of TBUFs:                        2  out of    768     0%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+XLXI_2_comp:Q                      | NONE                   | 32    |XLXN_3(XLXI_6_I3_0:O)              | NONE(*)(XLXI_3_i_2)    | 3     |XLXN_113(XLXI_1_I3_0:O)            | NONE(*)(XLXI_5_COUNT_1_1)| 52    |CLK                                | BUFGP                  | 35    |XLXI_2_rstcode:Q                   | NONE                   | 32    |-----------------------------------+------------------------+-------+(*) These 2 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -6   Minimum period: 8.597ns (Maximum Frequency: 116.320MHz)   Minimum input arrival time before clock: 9.657ns   Maximum output required time after clock: 13.467ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'XLXI_6_I3_0:O'Delay:               5.538ns (Levels of Logic = 1)  Source:            XLXI_3_i_0 (FF)  Destination:       XLXI_3_i_2 (FF)  Source Clock:      XLXI_6_I3_0:O rising  Destination Clock: XLXI_6_I3_0:O rising  Data Path: XLXI_3_i_0 to XLXI_3_i_2                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDR:C->Q             27   1.085   3.195  XLXI_3_i_0 (XLXI_3_i_0)     LUT3:I1->O            1   0.549   0.000  XLXI_3_i_Madd__n0000_Mxor_Result<2>_Result1 (XLXI_3_i__n0000<2>)     FD:D                      0.709          XLXI_3_i_2    ----------------------------------------    Total                      5.538ns (2.343ns logic, 3.195ns route)                                       (42.3% logic, 57.7% route)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'XLXI_1_I3_0:O'Delay:               8.562ns (Levels of Logic = 3)  Source:            XLXI_2_keydrv_1 (FF)  Destination:       XLXI_2_value_0 (FF)  Source Clock:      XLXI_1_I3_0:O rising  Destination Clock: XLXI_1_I3_0:O rising  Data Path: XLXI_2_keydrv_1 to XLXI_2_value_0                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDS:C->Q             16   1.085   2.520  XLXI_2_keydrv_1 (XLXI_2_keydrv_1)     LUT4_D:I0->O          5   0.549   1.566  XLXI_2__n004621 (CHOICE1088)     LUT3_D:I0->O          1   0.549   1.035  XLXI_2__n0046145 (XLXI_2__n0046)     LUT4_L:I0->LO         1   0.549   0.000  XLXI_2__n0001<0>841 (N14778)     FDS:D                     0.709          XLXI_2_value_0    ----------------------------------------    Total                      8.562ns (3.441ns logic, 5.121ns route)                                       (40.2% logic, 59.8% route)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'CLK'Delay:               8.597ns (Levels of Logic = 3)  Source:            XLXI_1_a_1 (FF)  Destination:       XLXI_1_a_17 (FF)  Source Clock:      CLK rising  Destination Clock: CLK rising  Data Path: XLXI_1_a_1 to XLXI_1_a_17                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDR:C->Q              2   1.085   1.206  XLXI_1_a_1 (XLXI_1_a_1)     LUT4:I0->O            1   0.549   1.035  XLXI_1__n000150 (CHOICE1063)     LUT4_L:I3->LO         1   0.549   0.100  XLXI_1__n000154 (CHOICE1064)     LUT4:I3->O           19   0.549   2.790  XLXI_1__n000172 (XLXI_1__n0001)     FDR:R                     0.734          XLXI_1_a_0    ----------------------------------------    Total                      8.597ns (3.466ns logic, 5.131ns route)                                       (40.3% logic, 59.7% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_1_I3_0:O'Offset:              9.657ns (Levels of Logic = 5)  Source:            COL<2> (PAD)  Destination:       XLXI_2_value_0 (FF)  Destination Clock: XLXI_1_I3_0:O rising  Data Path: COL<2> to XLXI_2_value_0                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O            14   0.776   2.340  COL_2_IBUF (COL_2_IBUF)     LUT4:I2->O            1   0.549   1.035  XLXI_2__n004696_SW0 (N14864)     LUT3_D:I0->O          5   0.549   1.566  XLXI_2__n004696 (CHOICE1113)     LUT3_D:I1->O          1   0.549   1.035  XLXI_2__n0046145 (XLXI_2__n0046)     LUT4_L:I0->LO         1   0.549   0.000  XLXI_2__n0001<0>841 (N14778)     FDS:D                     0.709          XLXI_2_value_0    ----------------------------------------    Total                      9.657ns (3.681ns logic, 5.976ns route)                                       (38.1% logic, 61.9% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_1_I3_0:O'Offset:              11.712ns (Levels of Logic = 5)  Source:            XLXI_5_COUNT_7_0 (FF)  Destination:       Q<6> (PAD)  Source Clock:      XLXI_1_I3_0:O rising  Data Path: XLXI_5_COUNT_7_0 to Q<6>                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDPE:C->Q             4   1.085   1.440  XLXI_5_COUNT_7_0 (XLXI_5_COUNT_7_0)     LUT3:I2->O            1   0.549   0.000  XLXI_4_Mmux_Q_inst_lut3_01 (XLXI_4_Mmux_Q__net0)     MUXF5:I0->O           1   0.315   0.000  XLXI_4_Mmux_Q_inst_mux_f5_0 (XLXI_4_Mmux_Q__net2)     MUXF6:I0->O           7   0.316   1.755  XLXI_4_Mmux_Q_inst_mux_f6_0 (XLXN_22<0>)     LUT4:I0->O            1   0.549   1.035  XLXI_7_Mrom_Q_inst_lut4_01 (Q_0_OBUF)     OBUF:I->O                 4.668          Q_0_OBUF (Q<0>)    ----------------------------------------    Total                     11.712ns (7.482ns logic, 4.230ns route)                                       (63.9% logic, 36.1% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_6_I3_0:O'Offset:              13.467ns (Levels of Logic = 5)  Source:            XLXI_3_i_0 (FF)  Destination:       Q<6> (PAD)  Source Clock:      XLXI_6_I3_0:O rising  Data Path: XLXI_3_i_0 to Q<6>                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDR:C->Q             27   1.085   3.195  XLXI_3_i_0 (XLXI_3_i_0)     LUT3:I0->O            1   0.549   0.000  XLXI_4_Mmux_Q_inst_lut3_81 (XLXI_4_Mmux_Q__net14)     MUXF5:I0->O           1   0.315   0.000  XLXI_4_Mmux_Q_inst_mux_f5_4 (XLXI_4_Mmux_Q__net16)     MUXF6:I0->O           7   0.316   1.755  XLXI_4_Mmux_Q_inst_mux_f6_2 (XLXN_22<2>)     LUT4:I2->O            1   0.549   1.035  XLXI_7_Mrom_Q_inst_lut4_01 (Q_0_OBUF)     OBUF:I->O                 4.668          Q_0_OBUF (Q<0>)    ----------------------------------------    Total                     13.467ns (7.482ns logic, 5.985ns route)                                       (55.6% logic, 44.4% route)=========================================================================CPU : 7.70 / 9.48 s | Elapsed : 8.00 / 10.00 s --> Total memory usage is 63596 kilobytes