library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fpq10ms is
      Port (CLK:in std_logic;
	       CP:out std_logic);
end fpq10ms;

architecture Behavioral of fpq10ms is
  signal a:integer range 0 to 400000;
    begin
		process(CLK)
		begin
		  if(CLK'event and CLK='1') then
		     if a=399999 then
			       a<=0;
				else
				  a<=a+1;
				end if;
			 case a is
			 when 0     to  199999=>CP<='1';
			 when 200000 to  399999=>CP<='0';
			 when others =>CP<='Z';
			 end case;
			end if;
		 end process;
end Behavioral;