library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SE8 is
    Port ( CP : in std_logic;
           s: out std_logic_vector(2 downto 0));
end SE8;

architecture Behavioral of SE8 is
begin
  process(CP)
  variable i:std_logic_vector(2 downto 0);
  begin
	  if(CP='1' and CP'event) then
		   i:=i+1;
	  end if;
	     s<=i;
  end process;
end Behavioral;