{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 03 15:20:06 2006 " "Info: Processing started: Fri Mar 03 15:20:06 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off crc_32 -c crc_32 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off crc_32 -c crc_32" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "crc_32 EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design \"crc_32\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 0 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "50 50 " "Info: No exact pin location assignment(s) for 50 pins of 50 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[0\] " "Info: Pin crc_out\[0\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[0] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[1\] " "Info: Pin crc_out\[1\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[1] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[2\] " "Info: Pin crc_out\[2\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[2] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[3\] " "Info: Pin crc_out\[3\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[3] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[4\] " "Info: Pin crc_out\[4\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[4] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[5\] " "Info: Pin crc_out\[5\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[5] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[6\] " "Info: Pin crc_out\[6\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[6] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[7\] " "Info: Pin crc_out\[7\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[7] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[8\] " "Info: Pin crc_out\[8\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[8] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[9\] " "Info: Pin crc_out\[9\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[9] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[10\] " "Info: Pin crc_out\[10\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[10] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[11\] " "Info: Pin crc_out\[11\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[11] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[12\] " "Info: Pin crc_out\[12\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[12] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[13\] " "Info: Pin crc_out\[13\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[13] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[14\] " "Info: Pin crc_out\[14\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[14] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[15\] " "Info: Pin crc_out\[15\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[15] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[16\] " "Info: Pin crc_out\[16\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[16\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[16] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[17\] " "Info: Pin crc_out\[17\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[17\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[17] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[18\] " "Info: Pin crc_out\[18\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[18\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[18] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[19\] " "Info: Pin crc_out\[19\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[19\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[19] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[20\] " "Info: Pin crc_out\[20\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[20\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[20] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[21\] " "Info: Pin crc_out\[21\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[21\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[21] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[22\] " "Info: Pin crc_out\[22\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[22\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[22] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[23\] " "Info: Pin crc_out\[23\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[23\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[23] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[24\] " "Info: Pin crc_out\[24\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[24\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[24] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[25\] " "Info: Pin crc_out\[25\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[25\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[25] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[26\] " "Info: Pin crc_out\[26\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[26\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[26] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[27\] " "Info: Pin crc_out\[27\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[27\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[27] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[28\] " "Info: Pin crc_out\[28\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[28\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[28] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[29\] " "Info: Pin crc_out\[29\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[29\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[29] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[30\] " "Info: Pin crc_out\[30\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[30\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[30] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "crc_out\[31\] " "Info: Pin crc_out\[31\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "crc_out\[31\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { crc_out[31] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { crc_out[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { clk } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "reset_n " "Info: Pin reset_n not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reset_n" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { reset_n } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { reset_n } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[0\] " "Info: Pin data_in\[0\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[0] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[1\] " "Info: Pin data_in\[1\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[1] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[2\] " "Info: Pin data_in\[2\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[2] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[3\] " "Info: Pin data_in\[3\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[3] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[4\] " "Info: Pin data_in\[4\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[4] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[5\] " "Info: Pin data_in\[5\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[5] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[6\] " "Info: Pin data_in\[6\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[6] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[7\] " "Info: Pin data_in\[7\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[7] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[8\] " "Info: Pin data_in\[8\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[8] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[9\] " "Info: Pin data_in\[9\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[9] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[10\] " "Info: Pin data_in\[10\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[10] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[11\] " "Info: Pin data_in\[11\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[11] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[12\] " "Info: Pin data_in\[12\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[12] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[13\] " "Info: Pin data_in\[13\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[13] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[14\] " "Info: Pin data_in\[14\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[14] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[15\] " "Info: Pin data_in\[15\] not assigned to an exact location on the device" {  } { { "crc_32.v" "" { Text "E:/FPGA/crc_final/crc_32_16/crc_32.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "crc_32" "UNKNOWN" "V1" "E:/FPGA/crc_final/crc_32_16/db/crc_32.quartus_db" { Floorplan "E:/FPGA/crc_final/crc_32_16/" "" "" { data_in[15] } "NODE_NAME" } "" } } { "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" { Floorplan "E:/FPGA/crc_final/crc_32_16/crc_32.fld" "" "" { data_in[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}