Project Information                                       c:\pinlvji\cepin.rpt

MAX+plus II Compiler Report File
Version 10.23 07/09/2003
Compiled: 05/19/2007 10:56:40

Copyright (C) 1988-2003 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was unsuccessful


CEPIN


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

cepin     EPM7096QC100-7   4        64       0      284     188         No Fit

User Pins:                 4        64       0  



Project Information                                       c:\pinlvji\cepin.rpt

** PROJECT COMPILATION MESSAGES **

Error: Project does not fit in specified device(s)
Error: No fit found, generating Report File

(See individual chip error summaries for additional information)

Project Information                                       c:\pinlvji\cepin.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'bz' chosen for auto global Clock


Project Information                                       c:\pinlvji\cepin.rpt

** FILE HIERARCHY **



|lpm_add_sub:2989|
|lpm_add_sub:2989|addcore:adder|
|lpm_add_sub:2989|addcore:adder|addcore:adder0|
|lpm_add_sub:2989|altshift:result_ext_latency_ffs|
|lpm_add_sub:2989|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2989|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:3517|
|lpm_add_sub:3517|addcore:adder|
|lpm_add_sub:3517|addcore:adder|addcore:adder0|
|lpm_add_sub:3517|altshift:result_ext_latency_ffs|
|lpm_add_sub:3517|altshift:carry_ext_latency_ffs|
|lpm_add_sub:3517|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:4045|
|lpm_add_sub:4045|addcore:adder|
|lpm_add_sub:4045|addcore:adder|addcore:adder0|
|lpm_add_sub:4045|altshift:result_ext_latency_ffs|
|lpm_add_sub:4045|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4045|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:4573|
|lpm_add_sub:4573|addcore:adder|
|lpm_add_sub:4573|addcore:adder|addcore:adder0|
|lpm_add_sub:4573|altshift:result_ext_latency_ffs|
|lpm_add_sub:4573|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4573|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:5101|
|lpm_add_sub:5101|addcore:adder|
|lpm_add_sub:5101|addcore:adder|addcore:adder0|
|lpm_add_sub:5101|altshift:result_ext_latency_ffs|
|lpm_add_sub:5101|altshift:carry_ext_latency_ffs|
|lpm_add_sub:5101|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:5629|
|lpm_add_sub:5629|addcore:adder|
|lpm_add_sub:5629|addcore:adder|addcore:adder0|
|lpm_add_sub:5629|altshift:result_ext_latency_ffs|
|lpm_add_sub:5629|altshift:carry_ext_latency_ffs|
|lpm_add_sub:5629|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:6157|
|lpm_add_sub:6157|addcore:adder|
|lpm_add_sub:6157|addcore:adder|addcore:adder0|
|lpm_add_sub:6157|altshift:result_ext_latency_ffs|
|lpm_add_sub:6157|altshift:carry_ext_latency_ffs|
|lpm_add_sub:6157|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:6685|
|lpm_add_sub:6685|addcore:adder|
|lpm_add_sub:6685|addcore:adder|addcore:adder0|
|lpm_add_sub:6685|altshift:result_ext_latency_ffs|
|lpm_add_sub:6685|altshift:carry_ext_latency_ffs|
|lpm_add_sub:6685|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:9465|
|lpm_add_sub:9465|addcore:adder|
|lpm_add_sub:9465|addcore:adder|addcore:adder0|
|lpm_add_sub:9465|altshift:result_ext_latency_ffs|
|lpm_add_sub:9465|altshift:carry_ext_latency_ffs|
|lpm_add_sub:9465|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:9993|
|lpm_add_sub:9993|addcore:adder|
|lpm_add_sub:9993|addcore:adder|addcore:adder0|
|lpm_add_sub:9993|altshift:result_ext_latency_ffs|
|lpm_add_sub:9993|altshift:carry_ext_latency_ffs|
|lpm_add_sub:9993|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:10521|
|lpm_add_sub:10521|addcore:adder|
|lpm_add_sub:10521|addcore:adder|addcore:adder0|
|lpm_add_sub:10521|altshift:result_ext_latency_ffs|
|lpm_add_sub:10521|altshift:carry_ext_latency_ffs|
|lpm_add_sub:10521|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:11049|
|lpm_add_sub:11049|addcore:adder|
|lpm_add_sub:11049|addcore:adder|addcore:adder0|
|lpm_add_sub:11049|altshift:result_ext_latency_ffs|
|lpm_add_sub:11049|altshift:carry_ext_latency_ffs|
|lpm_add_sub:11049|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:11577|
|lpm_add_sub:11577|addcore:adder|
|lpm_add_sub:11577|addcore:adder|addcore:adder0|
|lpm_add_sub:11577|altshift:result_ext_latency_ffs|
|lpm_add_sub:11577|altshift:carry_ext_latency_ffs|
|lpm_add_sub:11577|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:12105|
|lpm_add_sub:12105|addcore:adder|
|lpm_add_sub:12105|addcore:adder|addcore:adder0|
|lpm_add_sub:12105|altshift:result_ext_latency_ffs|
|lpm_add_sub:12105|altshift:carry_ext_latency_ffs|
|lpm_add_sub:12105|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:12633|
|lpm_add_sub:12633|addcore:adder|
|lpm_add_sub:12633|addcore:adder|addcore:adder0|
|lpm_add_sub:12633|altshift:result_ext_latency_ffs|
|lpm_add_sub:12633|altshift:carry_ext_latency_ffs|
|lpm_add_sub:12633|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:13161|
|lpm_add_sub:13161|addcore:adder|
|lpm_add_sub:13161|addcore:adder|addcore:adder0|
|lpm_add_sub:13161|altshift:result_ext_latency_ffs|
|lpm_add_sub:13161|altshift:carry_ext_latency_ffs|
|lpm_add_sub:13161|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                              c:\pinlvji\cepin.rpt
cepin

***** Logic for device 'cepin' contains errors -- see ERROR SUMMARY.




Device: EPM7096QC100-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    MultiVolt I/O                              = OFF



Device-Specific Information:                              c:\pinlvji\cepin.rpt
cepin

** ERROR SUMMARY **

Error: Project requires too many (284/96) logic cells
Error: Project requires too many (259/96) shareable expanders


Device-Specific Information:                              c:\pinlvji\cepin.rpt
cepin

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   0/12(  0%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   0/12(  0%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     0/16(  0%)   0/12(  0%)   0/16(  0%)   0/36(  0%) 
D:    LC49 - LC64     0/16(  0%)   0/12(  0%)   0/16(  0%)   0/36(  0%) 
E:    LC65 - LC80     0/16(  0%)   0/12(  0%)   0/16(  0%)   0/36(  0%) 
F:    LC81 - LC96     0/16(  0%)   0/12(  0%)   0/16(  0%)   0/36(  0%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                             0/72     (  0%)
Total logic cells used:                          0/96     (  0%)
Total shareable expanders used:                  0/96     (  0%)
Total Turbo logic cells used:                  284/96     (295%)
Total shareable expanders not available (n/a):  71/96     ( 73%)
Average fan-in:                                  7.34
Total fan-in:                                  2086

Total input pins required:                       4
Total output pins required:                     64
Total bidirectional pins required:               0
Total logic cells required:                    284
Total flipflops required:                      193
Total product terms required:                  856
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:         188

Synthesized logic cells:                        75/  96   ( 78%)



Device-Specific Information:                              c:\pinlvji\cepin.rpt
cepin

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  ??      -   ??      INPUT  G            0      0   0    0    0    0    0  bz
  ??      -   ??      INPUT               0      0   0    0    0    0    1  cl
  ??      -   ??      INPUT               0      0   0    0    0    0   33  dc
  ??      -   ??      INPUT               0      0   0    0    0   64   65  rst


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.