--/*JISUAN．VHD*/--計(jì)算轉(zhuǎn)換模塊
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jisuan is
    Port (clk,rst:in std_logic;
	 		 bzclk,dcclk:in std_logic_vector(31 downto 0);
			 data:out std_logic_vector(31 downto 0);
			 dian:out integer range -10 to 10 );
end jisuan;

architecture Behavioral of jisuan is

component div is
    Port (clk,rst:in std_logic;
	 		 bei,chu:in std_logic_vector(31 downto 0);
			 shang:out std_logic_vector(31 downto 0);
			 dian:out integer range -10 to 10 );
end component div;
signal bei:std_logic_vector(31 downto 0);
signal chu,shang:std_logic_vector(31 downto 0);

begin
chu<=bzclk;
bei<=dcclk;
u1:div port map (clk=>clk,rst=>rst,bei=>bei,chu=>chu,shang=>shang,dian=>dian);

end Behavioral;