?? conter8.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--B1_32 is 74390:1|32 at LC8
B1_32_reg_input = VCC;
B1_32 = TFFE(B1_32_reg_input, !B1_33, !clr, , );
--B1_7 is 74390:1|7 at LC17
B1_7_reg_input = VCC;
B1_7 = TFFE(B1_7_reg_input, A1L2, !clr, , );
--A1L2 is 10~7 at SEXP17
A1L2 = EXP(enb & clk);
--B1_6 is 74390:1|6 at LC11
B1_6_reg_input = VCC;
B1_6 = TFFE(B1_6_reg_input, B1L5, !clr, , );
--B1L5 is 74390:1|20~7 at SEXP6
B1L5 = EXP(!B1_3 & B1_7);
--B1_5 is 74390:1|5 at LC16
B1_5_reg_input = VCC;
B1_5 = TFFE(B1_5_reg_input, !B1_6, !clr, , );
--B1_3 is 74390:1|3 at LC14
B1_3_p1_out = !B1_3 & B1_5 & B1_6;
B1_3_or_out = B1_3_p1_out;
B1_3_reg_input = B1_3_or_out;
B1_3 = DFFE(B1_3_reg_input, !B1_7, !clr, , );
--B1_34 is 74390:1|34 at LC13
B1_34_reg_input = VCC;
B1_34 = TFFE(B1_34_reg_input, A1L1, !clr, , );
--A1L1 is 0~9 at SEXP5
A1L1 = EXP(B1_3 & !B1_5 & !B1_6 & B1_7);
--B1_31 is 74390:1|31 at LC6
B1_31_p1_out = B1_33 & !B1_31 & B1_32;
B1_31_or_out = B1_31_p1_out;
B1_31_reg_input = B1_31_or_out;
B1_31 = DFFE(B1_31_reg_input, !B1_34, !clr, , );
--B1_33 is 74390:1|33 at LC5
B1_33_reg_input = VCC;
B1_33 = TFFE(B1_33_reg_input, B1L6, !clr, , );
--B1L6 is 74390:1|29~7 at SEXP3
B1L6 = EXP(B1_34 & !B1_31);
--A1L3 is 19~10 at LC3
A1L3_p1_out = B1_34 & !B1_33 & B1_31 & !B1_32 & B1_3 & !B1_5 & !B1_6 & B1_7;
A1L3_or_out = A1L3_p1_out;
A1L3 = A1L3_or_out;
--clr is clr at PIN_81
--operation mode is input
clr = INPUT();
--enb is enb at PIN_33
--operation mode is input
enb = INPUT();
--clk is clk at PIN_52
--operation mode is input
clk = INPUT();
--q[6] is q[6] at PIN_9
--operation mode is output
q[6] = OUTPUT(B1_32);
--q[0] is q[0] at PIN_22
--operation mode is output
q[0] = OUTPUT(B1_7);
--q[1] is q[1] at PIN_8
--operation mode is output
q[1] = OUTPUT(B1_6);
--q[2] is q[2] at PIN_4
--operation mode is output
q[2] = OUTPUT(B1_5);
--q[3] is q[3] at PIN_5
--operation mode is output
q[3] = OUTPUT(B1_3);
--q[4] is q[4] at PIN_6
--operation mode is output
q[4] = OUTPUT(B1_34);
--q[7] is q[7] at PIN_10
--operation mode is output
q[7] = OUTPUT(B1_31);
--q[5] is q[5] at PIN_11
--operation mode is output
q[5] = OUTPUT(B1_33);
--cout is cout at PIN_12
--operation mode is output
cout = OUTPUT(A1L3);
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