?? tf_ctro.map.rpt
字號:
Analysis & Synthesis report for tf_ctro
Tue May 15 18:35:16 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Logic Cells Representing Combinational Loops
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue May 15 18:35:16 2007 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; tf_ctro ;
; Top-level Entity Name ; tf_ctro ;
; Family ; MAX7000S ;
; Total macrocells ; 6 ;
; Total pins ; 4 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; tf_ctro ; tf_ctro ;
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+----------------------------------------------------------------------+-----------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
; tf_ctro.bdf ; yes ; User Block Diagram/Schematic File ; E:/ft_top/tf_ctro.bdf ;
; 7493.bdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/others/maxplus2/7493.bdf ;
; 74154.bdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/others/maxplus2/74154.bdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 6 ;
; Total registers ; 4 ;
; I/O pins ; 4 ;
; Maximum fan-out node ; 7493:2|16 ;
; Maximum fan-out ; 5 ;
; Total fan-out ; 20 ;
; Average fan-out ; 2.00 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |tf_ctro ; 6 ; 4 ; |tf_ctro ;
; |7493:2| ; 4 ; 0 ; |tf_ctro|7493:2 ;
+----------------------------+------------+------+---------------------+
+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops ;
+--------------------------------------------------------+---+
; Logic Cell Name ; ;
+--------------------------------------------------------+---+
; 7~0 ; ;
; 16~0 ; ;
; Number of logic cells representing combinational loops ; 2 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/ft_top/tf_ctro.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue May 15 18:35:15 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tf_ctro -c tf_ctro
Info: Found 1 design units, including 1 entities, in source file tf_ctro.bdf
Info: Found entity 1: tf_ctro
Info: Elaborating entity "tf_ctro" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/7493.bdf
Info: Found entity 1: 7493
Info: Elaborating entity "7493" for hierarchy "7493:2"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74154.bdf
Info: Found entity 1: 74154
Info: Elaborating entity "74154" for hierarchy "74154:14"
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 10 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 3 output pins
Info: Implemented 6 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 15 18:35:16 2007
Info: Elapsed time: 00:00:01
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