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--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--  XAPP 253 - Synthesizable DDR SDRAM Controller
--
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--
--  File name :       controller.vhd
--
--  Description :     
--                    Main DDR SDRAM controller block. This includes the following
--                    features:
--                    - The controller state machine that controls the 
--                    initialization process upon power up, as well as the 
--                    read, write, and refresh commands. 
--                    - Accepts and decodes the user commands.
--                    - Generates the address and Bank address signals
--                    - Generates control signals for other modules, including
--                    the control signals for the dqs_en block.
--
--  Date - revision : 05/01/2002
--
--  Author :          Lakshmi Gopalakrishnan
--
--  Contact : e-mail  hotline@xilinx.com
--            phone   + 1 800 255 7778 
--
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--              statutory or otherwise, and Xilinx specifically disclaims any 
--              implied warranties of merchantability, non-infringement, or 
--              fitness for a particular purpose. Xilinx does not warrant that 
--              the functions contained in these designs will meet your 
--              requirements, or that the operation of these designs will be 
--              uninterrupted or error free, or that defects in the Designs 
--              will be corrected. Furthermore, Xilinx does not warrant or 
--              make any representations regarding use or the results of the 
--              use of the designs in terms of correctness, accuracy, 
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--
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--  Copyright