-------------------------------------------------------------  File: core.vhd                                       ----  created : July 09,2001 15:00                         ----  mail to khaer@opencores.org                          -------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_SIGNED.all;entity core is	port (		clk        : in  STD_LOGIC;		x_in       : in  STD_LOGIC_VECTOR (15 downto 0);		y_in       : in  STD_LOGIC_VECTOR (15 downto 0);		octant_in  : in  STD_LOGIC_VECTOR (2 downto 0);		octant_out : out STD_LOGIC_VECTOR (2 downto 0);		radius     : out STD_LOGIC_VECTOR (19 downto 0);		angle      : out STD_LOGIC_VECTOR (18 downto 0)		);end core;architecture core of core is    	component stage is 		generic (iteration : integer);		port (			clk        : in  STD_LOGIC;			x_in       : in  STD_LOGIC_VECTOR (19 downto 0);			y_in       : in  STD_LOGIC_VECTOR (19 downto 0);			z_in       : in  STD_LOGIC_VECTOR (18 downto 0);			x_out      : out STD_LOGIC_VECTOR (19 downto 0);			y_out      : out STD_LOGIC_VECTOR (19 downto 0);			z_out      : out STD_LOGIC_VECTOR (18 downto 0);			octant_in  : in  STD_LOGIC_VECTOR (2 downto 0);			octant_out : out STD_LOGIC_VECTOR (2 downto 0)						);	end component stage;								   	type XYvect is array(0 to 15) of std_logic_vector (19 downto 0); 	type Zvect  is array(0 to 15) of std_logic_vector (18 downto 0); 	type Ovect  is array(0 to 15) of std_logic_vector (2 downto 0); 	signal rad    : std_logic_vector (19 downto 0); 	signal angl   : std_logic_vector (18 downto 0); 	signal octant : std_logic_vector (2 downto 0); 		signal X : XYvect;	signal Y : XYvect;	signal Z : Zvect;	signal O : Ovect;           		begin         		X(0)(19 downto 4) <= x_in ;	Y(0)(19 downto 4) <= y_in ;	L1:    for i in 0 to 3 generate x(0)(i) <='0'; end generate;	L2:    for i in 0 to 3 generate y(0)(i) <='0'; end generate;	Z(0) <= (others => '0'); 	O(0) <= octant_in;      		gst:for i in 1 to 15 generate		st : stage 		generic map( 			iteration => i			)		port map (			clk        => clk,			x_in       => X(i-1),			y_in       => Y(i-1),			z_in       => Z(i-1),			x_out      => X(i),			y_out      => y(i),			z_out      => z(i),			octant_in  => O(i-1),			octant_out =>O(i)			);	end generate;	radius     <= x(15);	angle      <= z(15);	octant_out <= o(15);    end core;