-------------------------------------------------------------  File: pre.vhd                                        ----  created : July 09,2001 15:00                         ----  mail to khaer@opencores.org                          -------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_SIGNED.all;entity pre is   	port (                       		clk    : in  std_logic;		x_in   : in  STD_LOGIC_VECTOR (15 downto 0);		y_in   : in  STD_LOGIC_VECTOR (15 downto 0);		octant : out STD_LOGIC_VECTOR (2 downto 0);		x_out  : out STD_LOGIC_VECTOR (15 downto 0);		y_out  : out STD_LOGIC_VECTOR (15 downto 0)		);end pre;architecture pre of pre issignal xint,xinta,xintb : std_logic_vector (15 downto 0);signal yint,yinta,yintb : std_logic_vector (15 downto 0);signal oct_int          : std_logic_vector (1 downto 0); begin                         		process(clk)    		variable xsign    : std_logic;		variable ysign    : std_logic;		variable xyswap   : std_logic;                variable oct_int1 : std_logic_vector (1 downto 0);	begin		if clk'event and clk='1' 			then			xinta <=  x_in;			xintb <= -x_in;			yinta <=  y_in;			yintb <= -y_in;			xsign := xinta(15);			ysign := yinta(15);			                       if ( xsign = '0' and ysign = '0' ) then                             xint    <= xinta;                             yint    <= yinta;                             oct_int <= "00";                         elsif ( xsign = '1' and ysign = '0') then                             xint    <= yinta;                             yint    <= xintb;                             oct_int <= "01";                         elsif ( xsign = '1' and ysign = '1' ) then                             xint    <= xintb;                             yint    <= yintb;                             oct_int <= "10";                         else                              xint    <= yintb;                             yint    <= xinta;                             oct_int <= "11";                        end if; 			if xint <= yint then  				x_out    <= yint; 				y_out    <= xint; 				xyswap   := '1'; 				oct_int1 := oct_int +1; 			else 				x_out    <= xint; 				y_out    <= yint; 				xyswap   := '0';  				oct_int1 := oct_int; 			end if;			   			                        octant <= (oct_int1 & xyswap);	   		end if;			end process;	end pre;