library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.p_index.all;

entity index is
  generic(width :integer :=10);
  port(data: in std_logic_vector(width-1 downto 0);
          q: out std_logic_vector(width-1 downto 0));
end index;
architecture rtl of index is

begin

   q<=Delta(data,p);
end rtl;