?? djdplj_top.map.rpt
字號:
Analysis & Synthesis report for djdplj_top
Sun May 20 17:10:17 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Failed - Sun May 20 17:10:17 2007 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; djdplj_top ;
; Top-level Entity Name ; djdplj_top ;
; Family ; Stratix ;
; Total logic elements ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; N/A until Partition Merge ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name ; djdplj_top ; djdplj_top ;
; Family name ; Stratix ; Stratix ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Stratix/Stratix GX ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; djdplj_top.vhd ; yes ; Other ; C:/FJASLDF/djdplj_top.vhd ;
; cepin.vhd ; yes ; Other ; C:/FJASLDF/cepin.vhd ;
; div.vhd ; yes ; Other ; C:/FJASLDF/div.vhd ;
+----------------------------------+-----------------+-----------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sun May 20 17:10:12 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off djdplj_top -c djdplj_top
Warning: Using design file djdplj_top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: djdplj_top-Behavioral
Info: Found entity 1: djdplj_top
Info: Elaborating entity "djdplj_top" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at djdplj_top.vhd(91): inferring latch(es) for signal or variable "dc1", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at djdplj_top.vhd(91): inferred latch for "dc1"
Warning: Using design file cepin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: cepin-Behavioral
Info: Found entity 1: cepin
Info: Elaborating entity "cepin" for hierarchy "cepin:u1"
Warning: Using design file div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: div-Behavioral
Info: Found entity 1: div
Info: Elaborating entity "div" for hierarchy "div:u2"
Error (10394): VHDL error at div.vhd(57): left bound of range must be a constant File: C:/FJASLDF/div.vhd Line: 57
Error (10346): VHDL error at syn_unsi.vhd(114): formal port or parameter "L" must have actual or default value File: d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd Line: 114
Error (10809): VHDL error at syn_unsi.vhd(115): prefix for attribute range must denote a constrained array type File: d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd Line: 115
Error (10658): VHDL Operator error at div.vhd(57): failed to evaluate call to operator ""+"" File: C:/FJASLDF/div.vhd Line: 57
Error (10346): VHDL error at syn_unsi.vhd(239): formal port or parameter "L" must have actual or default value File: d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd Line: 239
Error (10346): VHDL error at syn_unsi.vhd(239): formal port or parameter "R" must have actual or default value File: d:/quartus70_windows/quartus/libraries/vhdl/synopsys/syn_unsi.vhd Line: 239
Error (10658): VHDL Operator error at div.vhd(57): failed to evaluate call to operator "">="" File: C:/FJASLDF/div.vhd Line: 57
Error: Can't elaborate user hierarchy "div:u2" File: C:/FJASLDF/djdplj_top.vhd Line: 56
Error: Quartus II Analysis & Synthesis was unsuccessful. 8 errors, 4 warnings
Info: Allocated 133 megabytes of memory during processing
Error: Processing ended: Sun May 20 17:10:17 2007
Error: Elapsed time: 00:00:05
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -