// E:\FPGA\CLKGEN
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Thu Apr 05 11:33:31 2007
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

module wave;

	 UUT (
	);

	integer TX_FILE;
	integer TX_ERROR;

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
endmodule