?? xiaopro.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity xiaopro is
port(a,clk1:in std_logic;
b:out std_logic);
end xiaopro;
architecture xiao_arc of xiaopro is
signal tmp1:std_logic;
begin
process(clk1,a)
variable tmp3,tmp2:std_logic;
begin
if clk1'event and clk1='0' then
tmp1<=a;
tmp2:=tmp1;
tmp3:=not tmp2;
end if;
b<=tmp1 and tmp3 and clk1;
end process;
end xiao_arc;
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