library ieee;
use ieee.std_logic_1164.all;
entity fen is
port(clk:in std_logic;
clk1:out std_logic);
end fen;
architecture fen_arc of fen is
begin 
process(clk)
	variable cnt:integer range 0 to 9999;
	begin
		IF clk'event and clk='1' then
			if cnt=9999 then 
				cnt:=0;
				clk1<='1';
			else
				cnt:=cnt+1;
				clk1<='0';
			end if;
		end if;
	end process;
end fen_arc;