# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = T:\xprojects\coregen_examples\async_fifo\verilog\61i_async_fifo_v5_1_ver_iseSET speedgrade = -6SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = False# SET outputdirectory = T:\xprojects\coregen_examples\async_fifo\verilog\61i_async_fifo_v5_1_ver_iseSET device = xc2v40SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = cs144SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex2SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1# END Select# BEGIN ParametersCSET create_rpm=falseCSET read_acknowledge=trueCSET almost_empty_flag=trueCSET write_acknowledge=trueCSET memory_type=blockCSET read_acknowledge_sense=active_highCSET read_count_width=2CSET fifo_depth=15CSET component_name=my_async_fifoCSET write_count_width=2CSET write_count=trueCSET read_count=trueCSET write_error=trueCSET read_error=trueCSET read_error_sense=active_highCSET almost_full_flag=trueCSET write_acknowledge_sense=active_highCSET write_error_sense=active_highCSET input_data_width=16# END ParametersGENERATE