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VERSION 6.1
May 13, 2005
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The files in this example are only intended
to be used as a reference for those who are
familiar with Coregen and the other Xilinx
tools.  For more thorough documentation, please
see the Coregen User Guide:
http://toolbox.xilinx.com/docsan/xilinx7/books/manuals.htm
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FILES INCLUDED IN ZIP
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readme.txt - This readme file.
my_async_fifo.xco - Core parameter file
my_async_fifo.veo - Core VHDL instantiation template
my_async_fifo.v - Core VHDL simulation file (only for simulation)
my_async_fifo.edn - Core EIDF netlist (only for implementation)
design_top.v - Verilog toplevel
design_top_tb.tf - Verilog testfixture

Project Navigaor Only Files:
  61i_async_fifo_v6_1_ver.ise - Project Navigator project file


=============================================================
SIMULATION
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-------------------- MODELSIM ------------------------

* Before the simulation can be run, the XilinxCoreLib
library needs to be compiled.  Also, it has to have
been compiled after the installation of 7.1i or a later
IP UPDATE.  If this has not been done, please install
the latest IP UPDATE.  Then follow Xilinx Solution 2561.

* If using ModelSim XE (Xilinx Edition), the models
are precompiled.  Go to the following site and make
sure that the latest models have been downloaded:
http://support.xilinx.com/support/mxelibs/index.htm
Again, 7.1i or later is needed to run this simulation.

********************************
	MODELSIM WARNINGS
********************************
When running the command "vcom design_top.vhd", the
following warning occurs:
# WARNING[1]: design_top.vhd(80): No default binding
for component: "core_async_fifo". (No entity named
"core_async_fifo" was found)

This can be ignored.  See solution 7973.
********************************

Steps to Simulate:
1. Extract all of the files to the same directory.

2. Open ModelSim

3. Click File -> Change Directory

4. Select the Directory where the files were extracted

5. Type the following commands in the command prompt:
vlib work
vcom -93 -explicit my_async_fifo.v
vcom -93 -explicit design_top.v
vcom -93 -explicit design_top_tb.tf
vsim work.testbench
add wave *
run 20000 ns


-------------------- ISE PROJECT ------------------------
Steps to Simulate:
1.Unzip the downloaded to a user chosen directory
 
2.Open ISE and select "Open project" under the file menu 

3.Select the example_name.npl file found in the previously 
  unzipped directory

4.To view individual items of code, double click on the file in
  "Sources in Project" window

5.To functionally simulate the core, highlight the testbench, and
  double click the "Simulate Functional VHDL model" in the 
  "Processes for Current Source" window 


----------------- OTHER SIMULATORS -------------------

The exact commands for other simulators are not
provided in this file.  Please see the following
site for tutorials on using other simulators:
http://toolbox.xilinx.com/docsan/xilinx7/books/manuals.htm


=============================================================
ISE - Using Coregen
=============================================================
To use Coregen in ISE, please refer to the
following document:
ftp://ftp.xilinx.com/pub/documentation/misc/coregen_ise.pdf